Commit 265280b9 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: add CLKMGR changes for DCN32/321 



Add support for managing DCN3.2.x clocks.

v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dda4fb85

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+35 −0
Original line number Diff line number Diff line
@@ -172,4 +172,39 @@ AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_ 


AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316)



###############################################################################

# DCN32

###############################################################################

CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o



AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32))



ifdef CONFIG_X86

CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse

endif



ifdef CONFIG_PPC64

CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -maltivec

endif



ifdef CONFIG_CC_IS_GCC

ifeq ($(call cc-ifversion, -lt, 0701, y), y)

IS_OLD_GCC = 1

endif

CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float

endif



ifdef CONFIG_X86

ifdef IS_OLD_GCC

# Stack alignment mismatch, proceed with caution.

# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3

# (8B stack alignment).

CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mpreferred-stack-boundary=4

else

CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse2

endif

endif



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)



endif

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+16 −1
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#include "dcn31/dcn31_clk_mgr.h"

#include "dcn315/dcn315_clk_mgr.h"

#include "dcn316/dcn316_clk_mgr.h"

#include "dcn32/dcn32_clk_mgr.h"





int clk_mgr_helper_get_active_display_cnt(
@@ -316,8 +317,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
		return &clk_mgr->base.base;

	}

		break;

#endif

	case AMDGPU_FAMILY_GC_11_0_0: {

	    struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);



	    if (clk_mgr == NULL) {

		BREAK_TO_DEBUGGER();

		return NULL;

	    }



	    dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

	    return &clk_mgr->base;

	    break;

#endif

	}

	default:

		ASSERT(0); /* Unknown Asic */

		break;
@@ -360,6 +372,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) 
		dcn316_clk_mgr_destroy(clk_mgr);

		break;



	case AMDGPU_FAMILY_GC_11_0_0:

		dcn32_clk_mgr_destroy(clk_mgr);

		break;

	default:

		break;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+13 −2
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) 


	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
@@ -137,6 +137,14 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) 
	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

	clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;

	clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;

	clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;

	clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;

	clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;

	clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;

	clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;

	clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;



	/* Set D - MALL - SR enter and exit times adjusted for MALL */

	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
@@ -517,6 +525,8 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d 
	if (!clk_mgr->smu_present)

		return;



	/* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */



	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;



	for (i = 0; i < MAX_PIPES * 2; i++) {
@@ -620,6 +630,7 @@ void dcn3_clk_mgr_construct( 


void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

{

	if (clk_mgr->base.bw_params)

		kfree(clk_mgr->base.bw_params);



	if (clk_mgr->wm_range_table)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

+60 −0
Original line number Diff line number Diff line
@@ -26,6 +26,66 @@ 
#ifndef __DCN30_CLK_MGR_H__

#define __DCN30_CLK_MGR_H__



//CLK1_CLK_PLL_REQ

#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT

#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0

#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc

#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10

#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL

#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L

#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L

//CLK1_CLK0_DFS_CNTL

#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT                                                               0x0

#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK                                                                 0x0000007FL

/*DPREF clock related*/

#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0

#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL

#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0

#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL

#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0

#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL

#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0

#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL



//CLK3_0_CLK3_CLK_PLL_REQ

#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0

#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc

#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10

#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL

#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L

#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L



#define mmCLK0_CLK2_DFS_CNTL                            0x16C55

#define mmCLK00_CLK0_CLK2_DFS_CNTL                      0x16C55

#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E55

#define mmCLK02_CLK0_CLK2_DFS_CNTL                      0x17055



#define mmCLK0_CLK3_DFS_CNTL                            0x16C60

#define mmCLK00_CLK0_CLK3_DFS_CNTL                      0x16C60

#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E60

#define mmCLK02_CLK0_CLK3_DFS_CNTL                      0x17060

#define mmCLK03_CLK0_CLK3_DFS_CNTL                      0x17260



#define mmCLK0_CLK_PLL_REQ                              0x16C10

#define mmCLK00_CLK0_CLK_PLL_REQ                        0x16C10

#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E10

#define mmCLK02_CLK0_CLK_PLL_REQ                        0x17010

#define mmCLK03_CLK0_CLK_PLL_REQ                        0x17210



#define mmCLK1_CLK_PLL_REQ                              0x1B00D

#define mmCLK10_CLK1_CLK_PLL_REQ                        0x1B00D

#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D

#define mmCLK12_CLK1_CLK_PLL_REQ                        0x1B40D

#define mmCLK13_CLK1_CLK_PLL_REQ                        0x1B60D



#define mmCLK2_CLK_PLL_REQ                              0x17E0D



/*AMCLK*/



#define mmCLK11_CLK1_CLK0_DFS_CNTL                      0x1B23F

#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D



#endif

void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);



void dcn3_clk_mgr_construct(struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h

0 → 100644
+65 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#ifndef DALSMC_H

#define DALSMC_H



#define DALSMC_VERSION 0x1



// SMU Response Codes:

#define DALSMC_Result_OK                   0x1

#define DALSMC_Result_Failed               0xFF

#define DALSMC_Result_UnknownCmd           0xFE

#define DALSMC_Result_CmdRejectedPrereq    0xFD

#define DALSMC_Result_CmdRejectedBusy      0xFC



// Message Definitions:

#define DALSMC_MSG_TestMessage                    0x1

#define DALSMC_MSG_GetSmuVersion                  0x2

#define DALSMC_MSG_GetDriverIfVersion             0x3

#define DALSMC_MSG_GetMsgHeaderVersion            0x4

#define DALSMC_MSG_SetDalDramAddrHigh             0x5

#define DALSMC_MSG_SetDalDramAddrLow              0x6

#define DALSMC_MSG_TransferTableSmu2Dram          0x7

#define DALSMC_MSG_TransferTableDram2Smu          0x8

#define DALSMC_MSG_SetHardMinByFreq               0x9

#define DALSMC_MSG_SetHardMaxByFreq               0xA

#define DALSMC_MSG_GetDpmFreqByIndex              0xB

#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC

#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD

#define DALSMC_MSG_NumOfDisplays                  0xE

#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF

#define DALSMC_MSG_BacoAudioD3PME                 0x10

#define DALSMC_MSG_SetFclkSwitchAllow             0x11

#define DALSMC_MSG_SetCabForUclkPstate            0x12

#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13

#define DALSMC_Message_Count                      0x14



typedef enum {

	FCLK_SWITCH_DISALLOW,

	FCLK_SWITCH_ALLOW,

} FclkSwitchAllow_e;



#endif