Commit 25970c22 authored by Wenpeng Liang's avatar Wenpeng Liang Committed by Zheng Zengkai
Browse files

RDMA/hns: Delete redundant abnormal interrupt status 

mainline inclusion
from mainline-v5.12-rc1
commit 2371efab
category: feature
bugzilla: 174002
CVE:NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2371efab9794bdf845b03473858a90d65035e331

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The hardware supports only two types of abnormal interrupts.

Fixes: a5073d60 ("RDMA/hns: Add eq support of hip08")
Link: https://lore.kernel.org/r/1617354454-47840-5-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarwangsirong <wangsirong@huawei.com>
Reviewed-by: default avatarChunZhi Hu <huchunzhi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 1a31eb42

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+5 −14
Original line number Diff line number Diff line
@@ -6035,28 +6035,19 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 
		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);



		int_work = 1;

	} else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {

		dev_err(dev, "BUS ERR!\n");

	} else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) {

		dev_err(dev, "RAS interrupt!\n");



		int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;

		int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S;

		roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);



		int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;

		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);



		int_work = 1;

	} else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {

		dev_err(dev, "OTHER ERR!\n");



		int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;

		roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);



		int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;

		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);



		int_work = 1;

	} else

	} else {

		dev_err(dev, "There is no abnormal irq found!\n");

	}



	return IRQ_RETVAL(int_work);

}

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+1 −2
Original line number Diff line number Diff line
@@ -1966,8 +1966,7 @@ struct hns_roce_dip { 
#define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000



#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S	0

#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S		1

#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S	2

#define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S		1



#define HNS_ROCE_EQ_DB_CMD_AEQ			0x0

#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED		0x1