Commit 1a31eb42 authored by Yangyang Li's avatar Yangyang Li Committed by Zheng Zengkai
Browse files

RDMA/hns: Delete redundant condition judgment related to eq 

mainline inclusion
from mainline-v5.12-rc1
commit 714a597b
category: feature
bugzilla: 174002
CVE:NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=714a597baab099e728307768e3b5c3b82d7b2ce3

----------------------------------------------------------------------

The register value related to the eq interrupt depends only on
enable_flag, so the redundant condition judgment is deleted.

Fixes: a5073d60 ("RDMA/hns: Add eq support of hip08")
Link: https://lore.kernel.org/r/1617354454-47840-4-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarYangyang Li <liyangyang20@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarwangsirong <wangsirong@huawei.com>
Reviewed-by: default avatarChunZhi Hu <huchunzhi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent e8638bde

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+6 −21
Original line number Diff line number Diff line
@@ -6062,31 +6062,16 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 
}



static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,

					int eq_num, int enable_flag)

					int eq_num, u32 enable_flag)

{

	int i;



	if (enable_flag == EQ_ENABLE) {

	for (i = 0; i < eq_num; i++)

		roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +

				   i * EQ_REG_OFFSET,

				   HNS_ROCE_V2_VF_EVENT_INT_EN_M);

			   i * EQ_REG_OFFSET, enable_flag);



		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,

			   HNS_ROCE_V2_VF_ABN_INT_EN_M);

		roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,

			   HNS_ROCE_V2_VF_ABN_INT_CFG_M);

	} else {

		for (i = 0; i < eq_num; i++)

			roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +

				   i * EQ_REG_OFFSET,

				   HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);



		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,

			   HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);

		roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,

			   HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);

	}

	roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);

	roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);

}



static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)