Commit 2594b713 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v5.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu updates from Borislav Petkov:

 - New AMD models support

 - Allow MONITOR/MWAIT to be used for C1 state entry on Hygon too

 - Use the special RAPL CPUID bit to detect the functionality on AMD and
   Hygon instead of doing family matching.

 - Add support for new Intel microcode deprecating TSX on some models
   and do not enable kernel workarounds for those CPUs when TSX
   transactions always abort, as a result of that microcode update.

* tag 'x86_cpu_for_v5.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/tsx: Clear CPUID bits when TSX always force aborts
  x86/events/intel: Do not deploy TSX force abort workaround when TSX is deprecated
  x86/msr: Define new bits in TSX_FORCE_ABORT MSR
  perf/x86/rapl: Use CPUID bit on AMD and Hygon parts
  x86/cstate: Allow ACPI C1 FFH MWAIT use on Hygon systems
  x86/amd_nb: Add AMD family 19h model 50h PCI ids
  x86/cpu: Fix core name for Sapphire Rapids
parents f565b207 29364930

arch/x86/events/intel/core.c

+7 −1
Original line number Diff line number Diff line
@@ -6015,7 +6015,13 @@ __init int intel_pmu_init(void) 
		tsx_attr = hsw_tsx_events_attrs;

		intel_pmu_pebs_data_source_skl(pmem);



		if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {

		/*

		 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.

		 * TSX force abort hooks are not required on these systems. Only deploy

		 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.

		 */

		if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&

		   !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {

			x86_pmu.flags |= PMU_FL_TFA;

			x86_pmu.get_event_constraints = tfa_get_event_constraints;

			x86_pmu.enable_all = intel_tfa_pmu_enable_all;

arch/x86/events/rapl.c

+2 −4
Original line number Diff line number Diff line
@@ -764,13 +764,14 @@ static struct rapl_model model_spr = { 
	.rapl_msrs      = intel_rapl_spr_msrs,

};



static struct rapl_model model_amd_fam17h = {

static struct rapl_model model_amd_hygon = {

	.events		= BIT(PERF_RAPL_PKG),

	.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,

	.rapl_msrs      = amd_rapl_msrs,

};



static const struct x86_cpu_id rapl_model_match[] __initconst = {

	X86_MATCH_FEATURE(X86_FEATURE_RAPL,		&model_amd_hygon),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&model_snb),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&model_snbep),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&model_snb),
@@ -803,9 +804,6 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&model_spr),

	X86_MATCH_VENDOR_FAM(AMD,	0x17,		&model_amd_fam17h),

	X86_MATCH_VENDOR_FAM(HYGON,	0x18,		&model_amd_fam17h),

	X86_MATCH_VENDOR_FAM(AMD,	0x19,		&model_amd_fam17h),

	{},

};

MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);

arch/x86/include/asm/cpufeatures.h

+2 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ 
#define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */

#define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */

/* free					( 3*32+29) */

#define X86_FEATURE_RAPL		( 3*32+29) /* AMD/Hygon RAPL interface */

#define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */

#define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
@@ -378,6 +378,7 @@ 
#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */

#define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */

#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */

#define X86_FEATURE_RTM_ALWAYS_ABORT	(18*32+11) /* "" RTM transaction always aborts */

#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */

#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */

#define X86_FEATURE_HYBRID_CPU		(18*32+15) /* "" This part has CPUs of more than one type */

arch/x86/include/asm/intel-family.h

+2 −1
Original line number Diff line number Diff line
@@ -102,7 +102,8 @@ 


#define INTEL_FAM6_TIGERLAKE_L		0x8C	/* Willow Cove */

#define INTEL_FAM6_TIGERLAKE		0x8D	/* Willow Cove */

#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Willow Cove */



#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */



#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

arch/x86/include/asm/msr-index.h

+4 −0
Original line number Diff line number Diff line
@@ -772,6 +772,10 @@ 


#define MSR_TFA_RTM_FORCE_ABORT_BIT	0

#define MSR_TFA_RTM_FORCE_ABORT		BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)

#define MSR_TFA_TSX_CPUID_CLEAR_BIT	1

#define MSR_TFA_TSX_CPUID_CLEAR		BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)

#define MSR_TFA_SDV_ENABLE_RTM_BIT	2

#define MSR_TFA_SDV_ENABLE_RTM		BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)



/* P4/Xeon+ specific */

#define MSR_IA32_MCG_EAX		0x00000180