x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits (258f3b8c) · Commits · EulixOS / Software / Kernel

arch/x86/kernel/cpu/intel.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -722,6 +722,7 @@ static void init_intel(struct cpuinfo_x86 *c)
		else if (tsx_ctrl_state == TSX_CTRL_DISABLE)
		tsx_disable();
		else if (tsx_ctrl_state == TSX_CTRL_RTM_ALWAYS_ABORT)
		/* See comment over that function for more details. */
		tsx_clear_cpuid();

		split_lock_init();

arch/x86/kernel/cpu/tsx.c

+47 −7

Original line number	Diff line number	Diff line
		@@ -58,7 +58,7 @@ void tsx_enable(void)
		wrmsrl(MSR_IA32_TSX_CTRL, tsx);
		}

		static bool __init tsx_ctrl_is_supported(void)
		static bool tsx_ctrl_is_supported(void)
		{
		u64 ia32_cap = x86_read_arch_cap_msr();

		@@ -84,6 +84,44 @@ static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
		return TSX_CTRL_ENABLE;
		}

		/*
		* Disabling TSX is not a trivial business.
		*
		* First of all, there's a CPUID bit: X86_FEATURE_RTM_ALWAYS_ABORT
		* which says that TSX is practically disabled (all transactions are
		* aborted by default). When that bit is set, the kernel unconditionally
		* disables TSX.
		*
		* In order to do that, however, it needs to dance a bit:
		*
		* 1. The first method to disable it is through MSR_TSX_FORCE_ABORT and
		* the MSR is present only when two CPUID bits are set:
		*
		* - X86_FEATURE_RTM_ALWAYS_ABORT
		* - X86_FEATURE_TSX_FORCE_ABORT
		*
		* 2. The second method is for CPUs which do not have the above-mentioned
		* MSR: those use a different MSR - MSR_IA32_TSX_CTRL and disable TSX
		* through that one. Those CPUs can also have the initially mentioned
		* CPUID bit X86_FEATURE_RTM_ALWAYS_ABORT set and for those the same strategy
		* applies: TSX gets disabled unconditionally.
		*
		* When either of the two methods are present, the kernel disables TSX and
		* clears the respective RTM and HLE feature flags.
		*
		* An additional twist in the whole thing presents late microcode loading
		* which, when done, may cause for the X86_FEATURE_RTM_ALWAYS_ABORT CPUID
		* bit to be set after the update.
		*
		* A subsequent hotplug operation on any logical CPU except the BSP will
		* cause for the supported CPUID feature bits to get re-detected and, if
		* RTM and HLE get cleared all of a sudden, but, userspace did consult
		* them before the update, then funny explosions will happen. Long story
		* short: the kernel doesn't modify CPUID feature bits after booting.
		*
		* That's why, this function's call in init_intel() doesn't clear the
		* feature flags.
		*/
		void tsx_clear_cpuid(void)
		{
		u64 msr;
		@@ -97,6 +135,10 @@ void tsx_clear_cpuid(void)
		rdmsrl(MSR_TSX_FORCE_ABORT, msr);
		msr \|= MSR_TFA_TSX_CPUID_CLEAR;
		wrmsrl(MSR_TSX_FORCE_ABORT, msr);
		} else if (tsx_ctrl_is_supported()) {
		rdmsrl(MSR_IA32_TSX_CTRL, msr);
		msr \|= TSX_CTRL_CPUID_CLEAR;
		wrmsrl(MSR_IA32_TSX_CTRL, msr);
		}
		}

		@@ -106,13 +148,11 @@ void __init tsx_init(void)
		int ret;

		/*
		* Hardware will always abort a TSX transaction if both CPUID bits
		* RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are set. In this case, it is
		* better not to enumerate CPUID.RTM and CPUID.HLE bits. Clear them
		* here.
		* Hardware will always abort a TSX transaction when the CPUID bit
		* RTM_ALWAYS_ABORT is set. In this case, it is better not to enumerate
		* CPUID.RTM and CPUID.HLE bits. Clear them here.
		*/
		if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
		boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
		if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
		tsx_ctrl_state = TSX_CTRL_RTM_ALWAYS_ABORT;
		tsx_clear_cpuid();
		setup_clear_cpu_cap(X86_FEATURE_RTM);