Commit 25879d7b authored by Qingqing Zhuo's avatar Qingqing Zhuo Committed by Alex Deucher
Browse files

drm/amd/display: Clean FPGA code in dc 



[Why]
Drop dead code for Linux.

[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC

Reviewed-by: default avatarAriel Bernstein <eric.bernstein@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7e60ab4e

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

+8 −12
Original line number Diff line number Diff line
@@ -111,13 +111,11 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) 


	bp->funcs->set_dce_clock(bp, &dce_clk_params);



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

		if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)

			dmcu->funcs->set_psr_wait_loop(dmcu,

					actual_clock / 1000 / 7);

	}

	}



	clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;

	return actual_clock;
@@ -153,13 +151,11 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) 
		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;





	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

		if (clk_mgr->dfs_bypass_disp_clk != actual_clock)

			dmcu->funcs->set_psr_wait_loop(dmcu,

					actual_clock / 1000 / 7);

	}

	}



	clk_mgr->dfs_bypass_disp_clk = actual_clock;

	return actual_clock;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

+4 −6
Original line number Diff line number Diff line
@@ -135,13 +135,11 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di 
			VBIOSSMC_MSG_SetDispclkFreq,

			khz_to_mhz_ceil(requested_dispclk_khz));



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

		if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)

			dmcu->funcs->set_psr_wait_loop(dmcu,

					actual_dispclk_set_mhz / 7);

	}

	}



	return actual_dispclk_set_mhz * 1000;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+27 −31
Original line number Diff line number Diff line
@@ -531,6 +531,11 @@ void dcn20_clk_mgr_construct( 
		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg)

{

	int dprefclk_did;

	int target_div;

	uint32_t pll_req_reg;

	struct fixed31_32 pll_req;



	clk_mgr->base.ctx = ctx;

	clk_mgr->pp_smu = pp_smu;

	clk_mgr->base.funcs = &dcn2_funcs;
@@ -547,19 +552,12 @@ void dcn20_clk_mgr_construct( 


	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved



	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;

		clk_mgr->base.dentist_vco_freq_khz = 3850000;



	} else {

	/* DFS Slice 2 should be used for DPREFCLK */

		int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);

	dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);

	/* Convert DPREFCLK DFS Slice DID to actual divider */

		int target_div = dentist_get_divider_from_did(dprefclk_did);



	target_div = dentist_get_divider_from_did(dprefclk_did);

	/* get FbMult value */

		uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);

		struct fixed31_32 pll_req;

	pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);



	/* set up a fixed-point number

	 * this works because the int part is on the right edge of the register
@@ -582,7 +580,6 @@ void dcn20_clk_mgr_construct( 
	/* Calculate the DPREFCLK in kHz.*/

	clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR

		* clk_mgr->base.dentist_vco_freq_khz) / target_div;

	}

	//Integrated_info table does not exist on dGPU projects so should not be referenced

	//anywhere in code for dGPUs.

	//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
@@ -590,4 +587,3 @@ void dcn20_clk_mgr_construct( 


	dce_clock_read_ss_info(clk_mgr);

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

+8 −14
Original line number Diff line number Diff line
@@ -190,11 +190,6 @@ void dcn201_clk_mgr_construct(struct dc_context *ctx, 
	clk_mgr->dprefclk_ss_divider = 1000;

	clk_mgr->ss_on_dprefclk = false;



	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		dcn201_funcs.update_clocks = dcn2_update_clocks_fpga;

		clk_mgr->base.dprefclk_khz = 600000;

		clk_mgr->base.dentist_vco_freq_khz = 3000000;

	} else {

	clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);

	clk_mgr->base.dprefclk_khz *= 100;
@@ -206,7 +201,6 @@ void dcn201_clk_mgr_construct(struct dc_context *ctx, 


	if (clk_mgr->base.dentist_vco_freq_khz == 0)

		clk_mgr->base.dentist_vco_freq_khz = 3000000;

	}



	if (!debug->disable_dfs_bypass && bp->integrated_info)

		if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+33 −40
Original line number Diff line number Diff line
@@ -705,6 +705,7 @@ void rn_clk_mgr_construct( 
	struct dpm_clocks clock_table = { 0 };

	enum pp_smu_status status = 0;

	int is_green_sardine = 0;

	struct clk_log_info log_info = {0};



#if defined(CONFIG_DRM_AMD_DC_FP)

	is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
@@ -725,12 +726,6 @@ void rn_clk_mgr_construct( 


	clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);



	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;

		clk_mgr->base.dentist_vco_freq_khz = 3600000;

	} else {

		struct clk_log_info log_info = {0};



	clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);



	/* SMU Version 55.51.0 and up no longer have an issue
@@ -766,7 +761,6 @@ void rn_clk_mgr_construct( 
	}

	/* Saved clocks configured at boot for debug purposes */

	rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

	}



	clk_mgr->base.dprefclk_khz = 600000;

	dce_clock_read_ss_info(clk_mgr);
@@ -786,9 +780,8 @@ void rn_clk_mgr_construct( 
		}

	}



	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {

	/* enable powerfeatures when displaycount goes to 0 */

	if (clk_mgr->smu_ver >= 0x00371500)

		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);

}

}