Commit 7e60ab4e authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz 



[Description]
- Previously we wanted to apply extra 60us of prefetch for min DCFCLK
  (200Mhz), but DCFCLK can be calculated to be 201Mhz which underflows
  also without the extra prefetch
- Instead, apply the the extra 60us prefetch for any DCFCLK freq <=
  300Mhz

Reviewed-by: default avatarNevenko Stupar <nevenko.stupar@amd.com>
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent de231189

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+2 −2
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
					v->SwathHeightC[k],

					TWait,

					(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||

						v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?

						v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

							mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,

					/* Output */

					&v->DSTXAfterScaler[k],
@@ -3315,7 +3315,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
							v->swath_width_chroma_ub_this_state[k],

							v->SwathHeightYThisState[k],

							v->SwathHeightCThisState[k], v->TWait,

							(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?

							(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

									mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,



							/* Output */

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define BPP_BLENDED_PIPE 0xffffffff



#define MEM_STROBE_FREQ_MHZ 1600

#define MIN_DCFCLK_FREQ_MHZ 200

#define DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ 300

#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0



struct display_mode_lib;