Commit 242b0aae authored Nov 16, 2022 by Tina Zhang Committed by Joerg Roedel Nov 19, 2022

iommu/vt-d: Preset Access bit for IOVA in FL non-leaf paging entries



The A/D bits are preseted for IOVA over first level(FL) usage for both
kernel DMA (i.e, domain typs is IOMMU_DOMAIN_DMA) and user space DMA
usage (i.e., domain type is IOMMU_DOMAIN_UNMANAGED).

Presetting A bit in FL requires to preset the bit in every related paging
entries, including the non-leaf ones. Otherwise, hardware may treat this
as an error. For example, in a case of ECAP_REG.SMPWC==0, DMA faults might
occur with below DMAR fault messages (wrapped for line length) dumped.

 DMAR: DRHD: handling fault status reg 2
 DMAR: [DMA Read NO_PASID] Request device [aa:00.0] fault addr 0x10c3a6000
    [fault reason 0x90]
    SM: A/D bit update needed in first-level entry when set up in no snoop

Fixes: 289b3b00 ("iommu/vt-d: Preset A/D bits for user space DMA usage")
Cc: stable@vger.kernel.org
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Link: https://lore.kernel.org/r/20221113010324.1094483-1-tina.zhang@intel.com


Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20221116051544.26540-2-baolu.lu@linux.intel.com


Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent 094226ad

drivers/iommu/intel/iommu.c

+3 −5

Original line number	Diff line number	Diff line
		@@ -959,11 +959,9 @@ static struct dma_pte pfn_to_dma_pte(struct dmar_domain domain,

		domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
		pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) \| DMA_PTE_READ \| DMA_PTE_WRITE;
		if (domain_use_first_level(domain)) {
		pteval \|= DMA_FL_PTE_XD \| DMA_FL_PTE_US;
		if (iommu_is_dma_domain(&domain->domain))
		pteval \|= DMA_FL_PTE_ACCESS;
		}
		if (domain_use_first_level(domain))
		pteval \|= DMA_FL_PTE_XD \| DMA_FL_PTE_US \| DMA_FL_PTE_ACCESS;

		if (cmpxchg64(&pte->val, 0ULL, pteval))
		/* Someone else set it while we were thinking; use theirs. */
		free_pgtable_page(tmp_page);