Commit 289b3b00 authored by Lu Baolu's avatar Lu Baolu Committed by Joerg Roedel
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iommu/vt-d: Preset A/D bits for user space DMA usage 



We preset the access and dirty bits for IOVA over first level usage only
for the kernel DMA (i.e., when domain type is IOMMU_DOMAIN_DMA). We should
also preset the FL A/D for user space DMA usage. The idea is that even the
user space A/D bit memory write is unnecessary. We should avoid it to
minimize the overhead.

Suggested-by: default avatarSanjay Kumar <sanjay.k.kumar@intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210720013856.4143880-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20210818134852.1847070-6-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 792fb43c

drivers/iommu/intel/iommu.c

+3 −7
Original line number Diff line number Diff line
@@ -2334,14 +2334,10 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, 
	attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);

	attr |= DMA_FL_PTE_PRESENT;

	if (domain_use_first_level(domain)) {

		attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US;



		if (iommu_is_dma_domain(&domain->domain)) {

			attr |= DMA_FL_PTE_ACCESS;

		attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;

		if (prot & DMA_PTE_WRITE)

			attr |= DMA_FL_PTE_DIRTY;

	}

	}



	pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr;