Commit 235c6763 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: add DCN32/321 specific files for Display Core 



Add core DC support for DCN 3.2.x.

v2: squash in fixup (Alex)

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 265280b9

drivers/gpu/drm/amd/display/dc/dcn32/Makefile

0 → 100644
+37 −0
Original line number Diff line number Diff line 
#

# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved

#

#  All rights reserved.  This notice is intended as a precaution against

#  inadvertent publication and does not imply publication or any waiver

#  of confidentiality.  The year included in the foregoing notice is the

#  year of creation of the work.

#

#  Authors: AMD

#

# Makefile for dcn32.



DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \

		dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \

		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \

		dcn32_mpc.o



CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse



ifdef CONFIG_CC_IS_GCC

ifeq ($(call cc-ifversion, -lt, 0701, y), y)

IS_OLD_GCC = 1

endif

endif



ifdef IS_OLD_GCC

# Stack alignment mismatch, proceed with caution.

# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3

# (8B stack alignment).

CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4

else

CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2

endif



AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))



AMD_DISPLAY_FILES += $(AMD_DAL_DCN32)

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

0 → 100644
+299 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "reg_helper.h"

#include "core_types.h"

#include "dcn32_dccg.h"



#define TO_DCN_DCCG(dccg)\

	container_of(dccg, struct dcn_dccg, base)



#define REG(reg) \

	(dccg_dcn->regs->reg)



#undef FN

#define FN(reg_name, field_name) \

	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name



#define CTX \

	dccg_dcn->base.ctx

#define DC_LOGGER \

	dccg->ctx->logger



enum pixel_rate_div {

	PIXEL_RATE_DIV_BY_1 = 0,

	PIXEL_RATE_DIV_BY_2 = 1,

	PIXEL_RATE_DIV_BY_4 = 3

};



static void dccg32_set_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,

		enum pixel_rate_div k1,

		enum pixel_rate_div k2)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	switch (otg_inst) {

	case 0:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG0_PIXEL_RATE_DIVK1, k1,

				OTG0_PIXEL_RATE_DIVK2, k2);

		break;

	case 1:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG1_PIXEL_RATE_DIVK1, k1,

				OTG1_PIXEL_RATE_DIVK2, k2);

		break;

	case 2:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG2_PIXEL_RATE_DIVK1, k1,

				OTG2_PIXEL_RATE_DIVK2, k2);

		break;

	case 3:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG3_PIXEL_RATE_DIVK1, k1,

				OTG3_PIXEL_RATE_DIVK2, k2);

		break;

	default:

		BREAK_TO_DEBUGGER();

		return;

	}

}



static void dccg32_set_dtbclk_p_src(

		struct dccg *dccg,

		enum streamclk_source src,

		uint32_t otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	uint32_t p_src_sel = 0; /* selects dprefclk */

	if (src == DTBCLK0)

		p_src_sel = 2;  /* selects dtbclk0 */



	switch (otg_inst) {

	case 0:

		if (src == REFCLK)

			REG_UPDATE(DTBCLK_P_CNTL,

					DTBCLK_P0_EN, 0);

		else

			REG_UPDATE_2(DTBCLK_P_CNTL,

					DTBCLK_P0_SRC_SEL, p_src_sel,

					DTBCLK_P0_EN, 1);

		break;

	case 1:

		if (src == REFCLK)

			REG_UPDATE(DTBCLK_P_CNTL,

					DTBCLK_P1_EN, 0);

		else

			REG_UPDATE_2(DTBCLK_P_CNTL,

					DTBCLK_P1_SRC_SEL, p_src_sel,

					DTBCLK_P1_EN, 1);

		break;

	case 2:

		if (src == REFCLK)

			REG_UPDATE(DTBCLK_P_CNTL,

					DTBCLK_P2_EN, 0);

		else

			REG_UPDATE_2(DTBCLK_P_CNTL,

					DTBCLK_P2_SRC_SEL, p_src_sel,

					DTBCLK_P2_EN, 1);

		break;

	case 3:

		if (src == REFCLK)

			REG_UPDATE(DTBCLK_P_CNTL,

					DTBCLK_P3_EN, 0);

		else

			REG_UPDATE_2(DTBCLK_P_CNTL,

					DTBCLK_P3_SRC_SEL, p_src_sel,

					DTBCLK_P3_EN, 1);

		break;

	default:

		BREAK_TO_DEBUGGER();

		return;

	}



}



/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */

void dccg32_set_dtbclk_dto(

		struct dccg *dccg,

		int otg_inst,

		int pixclk_khz,

		int num_odm_segments,

		const struct dc_crtc_timing *timing)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	/* DTO Output Rate / Pixel Rate = 1/4 */

	int req_dtbclk_khz = pixclk_khz / 4;



	if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {

		uint32_t modulo, phase;



		// phase / modulo = dtbclk / dtbclk ref

		modulo = 0xffffffff;

		phase = (((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1) / dccg->ref_dtbclk_khz;



		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], modulo);

		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], phase);



		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

				DTBCLK_DTO_ENABLE[otg_inst], 1);



		REG_WAIT(OTG_PIXEL_RATE_CNTL[otg_inst],

				DTBCLKDTO_ENABLE_STATUS[otg_inst], 1,

				1, 100);



		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */

		dccg32_set_pixel_rate_div(dccg, otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);



		/* The recommended programming sequence to enable DTBCLK DTO to generate

		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should

		 * be set only after DTO is enabled

		 */

		REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

				PIPE_DTO_SRC_SEL[otg_inst], 2);



		dccg->dtbclk_khz[otg_inst] = req_dtbclk_khz;

	} else {

		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],

				DTBCLK_DTO_ENABLE[otg_inst], 0,

				PIPE_DTO_SRC_SEL[otg_inst], 1);



		REG_WRITE(DTBCLK_DTO_MODULO[otg_inst], 0);

		REG_WRITE(DTBCLK_DTO_PHASE[otg_inst], 0);



		dccg->dtbclk_khz[otg_inst] = 0;

	}

}



static void dccg32_get_dccg_ref_freq(struct dccg *dccg,

		unsigned int xtalin_freq_inKhz,

		unsigned int *dccg_ref_freq_inKhz)

{

	/*

	 * Assume refclk is sourced from xtalin

	 * expect 100MHz

	 */

	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;

	return;

}



void dccg32_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	/* set the dtbclk_p source */

	dccg32_set_dtbclk_p_src(dccg, src, otg_inst);



	/* enabled to select one of the DTBCLKs for pipe */

	switch (otg_inst)

	{

	case 0:

		REG_UPDATE_2(DPSTREAMCLK_CNTL,

			     DPSTREAMCLK0_EN,

			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0);

		break;

	case 1:

		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,

			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1);

		break;

	case 2:

		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,

			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2);

		break;

	case 3:

		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,

			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3);

		break;

	default:

		BREAK_TO_DEBUGGER();

		return;

	}

}



void dccg32_otg_add_pixel(struct dccg *dccg,

		uint32_t otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_ADD_PIXEL[otg_inst], 1);

}



void dccg32_otg_drop_pixel(struct dccg *dccg,

		uint32_t otg_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

			OTG_DROP_PIXEL[otg_inst], 1);

}



static const struct dccg_funcs dccg32_funcs = {

	.update_dpp_dto = dccg2_update_dpp_dto,

	.get_dccg_ref_freq = dccg32_get_dccg_ref_freq,

	.dccg_init = dccg31_init,

	.set_dpstreamclk = dccg32_set_dpstreamclk,

	.enable_symclk32_se = dccg31_enable_symclk32_se,

	.disable_symclk32_se = dccg31_disable_symclk32_se,

	.enable_symclk32_le = dccg31_enable_symclk32_le,

	.disable_symclk32_le = dccg31_disable_symclk32_le,

	.set_physymclk = dccg31_set_physymclk,

	.set_dtbclk_dto = dccg32_set_dtbclk_dto,

	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,

	.otg_add_pixel = dccg32_otg_add_pixel,

	.otg_drop_pixel = dccg32_otg_drop_pixel,

};



struct dccg *dccg32_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *dccg_shift,

	const struct dccg_mask *dccg_mask)

{

	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);

	struct dccg *base;



	if (dccg_dcn == NULL) {

		BREAK_TO_DEBUGGER();

		return NULL;

	}



	base = &dccg_dcn->base;

	base->ctx = ctx;

	base->funcs = &dccg32_funcs;



	dccg_dcn->regs = regs;

	dccg_dcn->dccg_shift = dccg_shift;

	dccg_dcn->dccg_mask = dccg_mask;



	return &dccg_dcn->base;

}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h

0 → 100644
+155 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DCN32_DCCG_H__

#define __DCN32_DCCG_H__



#include "dcn31/dcn31_dccg.h"



#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix





#define DCCG_REG_LIST_DCN32() \

	SR(DPPCLK_DTO_CTRL),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\

	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\

	SR(PHYASYMCLK_CLOCK_CNTL),\

	SR(PHYBSYMCLK_CLOCK_CNTL),\

	SR(PHYCSYMCLK_CLOCK_CNTL),\

	SR(PHYDSYMCLK_CLOCK_CNTL),\

	SR(PHYESYMCLK_CLOCK_CNTL),\

	SR(DPSTREAMCLK_CNTL),\

	SR(SYMCLK32_SE_CNTL),\

	SR(SYMCLK32_LE_CNTL),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\

	DCCG_SRII(MODULO, DTBCLK_DTO, 0),\

	DCCG_SRII(MODULO, DTBCLK_DTO, 1),\

	DCCG_SRII(MODULO, DTBCLK_DTO, 2),\

	DCCG_SRII(MODULO, DTBCLK_DTO, 3),\

	DCCG_SRII(PHASE, DTBCLK_DTO, 0),\

	DCCG_SRII(PHASE, DTBCLK_DTO, 1),\

	DCCG_SRII(PHASE, DTBCLK_DTO, 2),\

	DCCG_SRII(PHASE, DTBCLK_DTO, 3),\

	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\

	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\

	SR(OTG_PIXEL_RATE_DIV),\

	SR(DTBCLK_P_CNTL),\

	SR(DCCG_AUDIO_DTO_SOURCE)





#define DCCG_MASK_SH_LIST_DCN32(mask_sh) \

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\

	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\

	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\

	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\

	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\

	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\

	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\

	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\

	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\

	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)





struct dccg *dccg32_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *dccg_shift,

	const struct dccg_mask *dccg_mask);



#endif //__DCN32_DCCG_H__

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c

0 → 100644
+283 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h

0 → 100644
+42 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 *  and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DC_LINK_ENCODER__DCN32_H__

#define __DC_LINK_ENCODER__DCN32_H__



#include "dcn30/dcn30_dio_link_encoder.h"



void dcn32_link_encoder_construct(

	struct dcn20_link_encoder *enc20,

	const struct encoder_init_data *init_data,

	const struct encoder_feature_support *enc_features,

	const struct dcn10_link_enc_registers *link_regs,

	const struct dcn10_link_enc_aux_registers *aux_regs,

	const struct dcn10_link_enc_hpd_registers *hpd_regs,

	const struct dcn10_link_enc_shift *link_shift,

	const struct dcn10_link_enc_mask *link_mask);





#endif /* __DC_LINK_ENCODER__DCN32_H__ */