Commit 216e2aed authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - Errata workarounds for Cortex-A510: broken hardware dirty bit
   management, detection code for the TRBE (tracing) bugs with the
   actual fixes going in via the CoreSight tree.

 - Cortex-X2 errata handling for TRBE (inheriting the workarounds from
   Cortex-A710).

 - Fix ex_handler_load_unaligned_zeropad() to use the correct struct
   members.

 - A couple of kselftest fixes for FPSIMD.

 - Silence the vdso "no previous prototype" warning.

 - Mark start_backtrace() notrace and NOKPROBE_SYMBOL.

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: cpufeature: List early Cortex-A510 parts as having broken dbm
  kselftest/arm64: Correct logging of FPSIMD register read via ptrace
  kselftest/arm64: Skip VL_INHERIT tests for unsupported vector types
  arm64: errata: Add detection for TRBE trace data corruption
  arm64: errata: Add detection for TRBE invalid prohibited states
  arm64: errata: Add detection for TRBE ignored system register writes
  arm64: Add Cortex-A510 CPU part definition
  arm64: extable: fix load_unaligned_zeropad() reg indices
  arm64: Mark start_backtrace() notrace and NOKPROBE_SYMBOL
  arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges
  arm64: Add Cortex-X2 CPU part definition
  arm64: vdso: Fix "no previous prototype" warning
parents d1e7f091 297ae1eb

Documentation/arm64/silicon-errata.rst

+12 −0
Original line number Diff line number Diff line
@@ -52,6 +52,12 @@ stable kernels. 
| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2038923        | ARM64_ERRATUM_2038923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #1902691        | ARM64_ERRATUM_1902691       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |
@@ -92,12 +98,18 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2051678        | ARM64_ERRATUM_2051678       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+75 −6
Original line number Diff line number Diff line
@@ -670,15 +670,25 @@ config ARM64_ERRATUM_1508412 
config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	bool



config ARM64_ERRATUM_2051678

	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"

	help

	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.

	  Affected Coretex-A510 might not respect the ordering rules for

	  hardware update of the page table's dirty bit. The workaround

	  is to not enable the feature on affected CPUs.



	  If unsure, say Y.



config ARM64_ERRATUM_2119858

	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"

	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.

	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.



	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace

	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.
@@ -761,14 +771,14 @@ config ARM64_ERRATUM_2253138 
	  If unsure, say Y.



config ARM64_ERRATUM_2224489

	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"

	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.

	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.



	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved

	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
@@ -778,6 +788,65 @@ config ARM64_ERRATUM_2224489 


	  If unsure, say Y.



config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.



	  Affected Cortex-A510 core might fail to write into system registers after the

	  TRBE has been disabled. Under some conditions after the TRBE has been disabled

	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,

	  and TRBTRG_EL1 will be ignored and will not be effected.



	  Work around this in the driver by executing TSB CSYNC and DSB after collection

	  is stopped and before performing a system register write to one of the affected

	  registers.



	  If unsure, say Y.



config ARM64_ERRATUM_2038923

	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.



	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is

	  prohibited within the CPU. As a result, the trace buffer or trace buffer state

	  might be corrupted. This happens after TRBE buffer has been enabled by setting

	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before

	  execution changes from a context, in which trace is prohibited to one where it

	  isn't, or vice versa. In these mentioned conditions, the view of whether trace

	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or

	  the trace buffer state might be corrupted.



	  Work around this in the driver by preventing an inconsistent view of whether the

	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a

	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or

	  two ISB instructions if no ERET is to take place.



	  If unsure, say Y.



config ARM64_ERRATUM_1902691

	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.



	  Affected Cortex-A510 core might cause trace data corruption, when being written

	  into the memory. Effectively TRBE is broken and hence cannot be used to capture

	  trace data.



	  Work around this problem in the driver by just preventing TRBE initialization on

	  affected cpus. The firmware must have disabled the access to TRBE for the kernel

	  on such implementations. This will cover the kernel for any firmware that doesn't

	  do this already.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -73,7 +73,9 @@ 
#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49



#define APM_CPU_PART_POTENZA		0x000
@@ -115,7 +117,9 @@ 
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

arch/arm64/kernel/cpu_errata.c

+29 −0
Original line number Diff line number Diff line
@@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_2119858

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),

#endif

	{},

};
@@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_2224489

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),

#endif

	{},

};
@@ -597,6 +599,33 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,

		CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2064142

	{

		.desc = "ARM erratum 2064142",

		.capability = ARM64_WORKAROUND_2064142,



		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2038923

	{

		.desc = "ARM erratum 2038923",

		.capability = ARM64_WORKAROUND_2038923,



		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1902691

	{

		.desc = "ARM erratum 1902691",

		.capability = ARM64_WORKAROUND_1902691,



		/* Cortex-A510 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)

	},

#endif

	{

	}

arch/arm64/kernel/cpufeature.c

+3 −0
Original line number Diff line number Diff line
@@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void) 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),

		/* Kryo4xx Silver (rdpe => r1p0) */

		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2051678

		MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),

#endif

		{},

	};