Commit 297ae1eb authored by James Morse's avatar James Morse Committed by Catalin Marinas
Browse files

arm64: cpufeature: List early Cortex-A510 parts as having broken dbm 



Versions of Cortex-A510 before r0p3 are affected by a hardware erratum
where the hardware update of the dirty bit is not correctly ordered.

Add these cpus to the cpu_has_broken_dbm list.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220125154040.549272-3-james.morse@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent df205970

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2051678        | ARM64_ERRATUM_2051678       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -670,6 +670,16 @@ config ARM64_ERRATUM_1508412 
config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	bool



config ARM64_ERRATUM_2051678

	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"

	help

	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.

	  Affected Coretex-A510 might not respect the ordering rules for

	  hardware update of the page table's dirty bit. The workaround

	  is to not enable the feature on affected CPUs.



	  If unsure, say Y.



config ARM64_ERRATUM_2119858

	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

arch/arm64/kernel/cpufeature.c

+3 −0
Original line number Diff line number Diff line
@@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void) 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),

		/* Kryo4xx Silver (rdpe => r1p0) */

		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2051678

		MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),

#endif

		{},

	};