Commit 21047e91 authored by Catalin Marinas's avatar Catalin Marinas Committed by Will Deacon
Browse files

arm64: Check if GMID_EL1.BS is the same on all CPUs 



The GMID_EL1.BS field determines the number of tags accessed by the
LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
zeroing page tags.

Taint the kernel if GMID_EL1.BS differs between CPUs but only of
CONFIG_ARM64_MTE is enabled.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Link: https://lore.kernel.org/r/20210526193621.21559-3-catalin.marinas@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 7513cc8a

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ struct cpuinfo_arm64 { 
	u64		reg_dczid;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_gmid;



	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr1;

arch/arm64/include/asm/cpufeature.h

+7 −0
Original line number Diff line number Diff line
@@ -619,6 +619,13 @@ static inline bool id_aa64pfr0_sve(u64 pfr0) 
	return val > 0;

}



static inline bool id_aa64pfr1_mte(u64 pfr1)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);



	return val >= ID_AA64PFR1_MTE;

}



void __init setup_cpu_features(void);

void check_local_cpu_capabilities(void);

arch/arm64/kernel/cpufeature.c

+21 −0
Original line number Diff line number Diff line
@@ -400,6 +400,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_gmid[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
@@ -617,6 +622,9 @@ static const struct __ftr_reg_entry { 
	/* Op1 = 0, CRn = 1, CRm = 2 */

	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),



	/* Op1 = 1, CRn = 0, CRm = 0 */

	ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),



	/* Op1 = 3, CRn = 0, CRm = 0 */

	{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },

	ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
@@ -911,6 +919,9 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
		sve_init_vq_map();

	}



	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))

		init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);



	/*

	 * Initialize the indirect array of CPU hwcaps capabilities pointers

	 * before we handle the boot CPU below.
@@ -1134,6 +1145,16 @@ void update_cpu_features(int cpu, 
			sve_update_vq_map();

	}



	/*

	 * The kernel uses the LDGM/STGM instructions and the number of tags

	 * they read/write depends on the GMID_EL1.BS field. Check that the

	 * value is the same on all CPUs.

	 */

	if (IS_ENABLED(CONFIG_ARM64_MTE) &&

	    id_aa64pfr1_mte(info->reg_id_aa64pfr1))

		taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,

					      info->reg_gmid, boot->reg_gmid);



	/*

	 * This relies on a sanitised view of the AArch64 ID registers

	 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.

arch/arm64/kernel/cpuinfo.c

+3 −0
Original line number Diff line number Diff line
@@ -371,6 +371,9 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);

	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);



	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))

		info->reg_gmid = read_cpuid(GMID_EL1);



	/* Update the 32bit ID registers only if AArch32 is implemented */

	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

		info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);