Unverified Commit 204637ec authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.18-next-dts32' of... 

Merge tag 'v5.18-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Delete no longer needed properties of MediaTek Larbs for MT2701.

* tag 'v5.18-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm: dts: mediatek: Get rid of mediatek, larb for MM nodes

Link: https://lore.kernel.org/r/b4383f23-0adc-b9de-a1d9-abd1c2f82b27@gmail.com

This concludes a cleanup that was started back in 2019, with an
incompatible DT binding change. Kernels before 5.18 can no longer
use the updated dtb from 5.19, and the drivers no longer parse the
old properties, which breaks compatibility with older dtb files.

Link: https://lore.kernel.org/lkml/1546318276-18993-2-git-send-email-yong.wu@mediatek.com/


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 8f311c09 a044e6a0

arch/arm/boot/dts/mt2701.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -564,7 +564,6 @@ 
		clock-names = "jpgdec-smi",

			      "jpgdec";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,

			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;

	};
@@ -577,7 +576,6 @@ 
		clocks =  <&imgsys CLK_IMG_VENC>;

		clock-names = "jpgenc";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,

			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;

	};

arch/arm/boot/dts/mt7623n.dtsi

+0 −5
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ 
		clock-names = "jpgdec-smi",

			      "jpgdec";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,

			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;

	};
@@ -144,7 +143,6 @@ 
		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_OVL>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;

		mediatek,larb = <&larb0>;

	};



	rdma0: rdma@14008000 {
@@ -154,7 +152,6 @@ 
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_RDMA>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;

		mediatek,larb = <&larb0>;

	};



	wdma@14009000 {
@@ -164,7 +161,6 @@ 
		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_WDMA>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;

		mediatek,larb = <&larb0>;

	};



	bls: pwm@1400a000 {
@@ -215,7 +211,6 @@ 
		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_RDMA1>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;

		mediatek,larb = <&larb0>;

	};



	dpi0: dpi@14014000 {