Unverified Commit 1f66f63c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-fixes-5.19-2' of... 

Merge tag 'imx-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.19, round 2:

- Fix the SDIO description for imx7d-smegw01 board to ensure there is
  no communication made at 1.8V.
- Fix pgc_ispdwp power-domain clock, which should be
  IMX8MP_CLK_MEDIA_ISP_ROOT.
- Re-enable framebuffer support in mxs_defconfig to fix a Kconfig
  regression.
- A series from Peng Fan (and Sherry Sun) fixing various pads on i.MX8MP
  based boards to leave reserved bits untouched.

* tag 'imx-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings
  arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
  arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings
  arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings
  arm64: dts: imx8mp-venice-gw74xx: correct pad settings
  arm64: dts: imx8mp-evk: correct I2C3 pad settings
  arm64: dts: imx8mp-evk: correct I2C1 pad settings
  arm64: dts: imx8mp-evk: correct I2C5 pad settings
  arm64: dts: imx8mp-evk: correct vbus pad settings
  arm64: dts: imx8mp-evk: correct eqos pad settings
  arm64: dts: imx8mp-evk: correct vbus pad settings
  arm64: dts: imx8mp-evk: correct gpio-led pad settings
  arm64: dts: imx8mp-evk: correct the uart2 pinctl value
  arm64: dts: imx8mp-evk: correct mmc pad settings
  ARM: mxs_defconfig: Enable the framebuffer
  arm64: dts: imx8mp: correct clock of pgc_ispdwp
  ARM: dts: imx7d-smegw01: Fix the SDIO description

Link: https://lore.kernel.org/r/20220629021244.GL819983@dragon


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a38dbb4f 8630354f

arch/arm/boot/dts/imx7d-smegw01.dts

+1 −3
Original line number Diff line number Diff line
@@ -216,10 +216,8 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc2>;

	bus-width = <4>;

	no-1-8-v;

	non-removable;

	cap-sd-highspeed;

	sd-uhs-ddr50;

	mmc-ddr-1_8v;

	vmmc-supply = <&reg_wifi>;

	enable-sdio-wakeup;

	status = "okay";

arch/arm/configs/mxs_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y 
CONFIG_DRM=y

CONFIG_DRM_PANEL_SEIKO_43WVF1G=y

CONFIG_DRM_MXSFB=y

CONFIG_FB=y

CONFIG_FB_MODE_HELPERS=y

CONFIG_LCD_CLASS_DEVICE=y

CONFIG_BACKLIGHT_CLASS_DEVICE=y

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+44 −44
Original line number Diff line number Diff line
@@ -395,41 +395,41 @@ 
&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10

		>;

	};



	pinctrl_fec: fecgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3

			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f

			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2

			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16

			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10

		>;

	};
@@ -461,28 +461,28 @@ 


	pinctrl_gpio_led: gpioledgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19

			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3

			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3

			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2

			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2

		>;

	};



	pinctrl_i2c3: i2c3grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2

		>;

	};



	pinctrl_i2c5: i2c5grp {

		fsl,pins = <

			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c3

			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c3

			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2

			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2

		>;

	};
@@ -500,20 +500,20 @@ 


	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140

		>;

	};



	pinctrl_usb1_vbus: usb1grp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x19

			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10

		>;

	};
@@ -525,7 +525,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -537,7 +537,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0

		>;

	};
@@ -549,7 +549,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0

		>;

	};

arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts

+20 −20
Original line number Diff line number Diff line
@@ -110,28 +110,28 @@ 
&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x19

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40

		>;

	};
@@ -151,7 +151,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -163,13 +163,13 @@ 


	pinctrl_reg_usb1: regusb1grp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19

			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10

		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};

};

arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

+24 −24
Original line number Diff line number Diff line
@@ -116,48 +116,48 @@ 
&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2

		>;

	};



	pinctrl_i2c2_gpio: i2c2gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e3

			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e3

			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2

			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2

		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x49

			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x49

			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x40

			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x40

		>;

	};
@@ -175,7 +175,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -187,7 +187,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -199,7 +199,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};

};