Commit 1f1c42ec authored by Rick Wertenbroek's avatar Rick Wertenbroek Committed by Lorenzo Pieralisi
Browse files

PCI: rockchip: Write PCI Device ID to correct register 

Write PCI Device ID (DID) to the correct register. The Device ID was not
updated through the correct register. Device ID was written to a read-only
register and therefore did not work. The Device ID is now set through the
correct register. This is documented in the RK3399 TRM section 17.6.6.1.1

Link: https://lore.kernel.org/r/20230418074700.1083505-3-rick.wertenbroek@gmail.com


Fixes: cf590b07 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Tested-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Signed-off-by: default avatarRick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
parent 92a9c57c

drivers/pci/controller/pcie-rockchip-ep.c

+4 −2
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, 
static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,

					 struct pci_epf_header *hdr)

{

	u32 reg;

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;
@@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, 
				    PCIE_CORE_CONFIG_VENDOR);

	}



	rockchip_pcie_write(rockchip, hdr->deviceid << 16,

			    ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);

	reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);

	reg = (reg & 0xFFFF) | (hdr->deviceid << 16);

	rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);



	rockchip_pcie_write(rockchip,

			    hdr->revid |

drivers/pci/controller/pcie-rockchip.h

+2 −0
Original line number Diff line number Diff line
@@ -133,6 +133,8 @@ 
#define PCIE_RC_RP_ATS_BASE		0x400000

#define PCIE_RC_CONFIG_NORMAL_BASE	0x800000

#define PCIE_RC_CONFIG_BASE		0xa00000

#define PCIE_EP_CONFIG_BASE		0xa00000

#define PCIE_EP_CONFIG_DID_VID		(PCIE_EP_CONFIG_BASE + 0x00)

#define PCIE_RC_CONFIG_RID_CCR		(PCIE_RC_CONFIG_BASE + 0x08)

#define PCIE_RC_CONFIG_DCR		(PCIE_RC_CONFIG_BASE + 0xc4)

#define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT		18