Commit 1e32084c authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Rob Herring
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dt-bindings: fpga: zynq: convert bindings to YAML 



Convert FPGA for Xilinx Zynq SoC bindings documentation to YAML.

Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Link: https://lore.kernel.org/r/20210613212856.296153-1-iwamatsu@nigauri.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent b14e889c

Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt

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Xilinx Zynq FPGA Manager



Required properties:

- compatible:		should contain "xlnx,zynq-devcfg-1.0"

- reg:			base address and size for memory mapped io

- interrupts:		interrupt for the FPGA manager device

- clocks:		phandle for clocks required operation

- clock-names:		name for the clock, should be "ref_clk"

- syscon:		phandle for access to SLCR registers



Example:

	devcfg: devcfg@f8007000 {

		compatible = "xlnx,zynq-devcfg-1.0";

		reg = <0xf8007000 0x100>;

		interrupts = <0 8 4>;

		clocks = <&clkc 12>;

		clock-names = "ref_clk";

		syscon = <&slcr>;

	};

Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx Zynq FPGA Manager Device Tree Bindings



maintainers:

  - Michal Simek <michal.simek@xilinx.com>



properties:

  compatible:

    const: xlnx,zynq-devcfg-1.0



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: ref_clk



  syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to syscon block which provide access to SLCR registers



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - syscon



additionalProperties: false



examples:

  - |

    devcfg: devcfg@f8007000 {

      compatible = "xlnx,zynq-devcfg-1.0";

      reg = <0xf8007000 0x100>;

      interrupts = <0 8 4>;

      clocks = <&clkc 12>;

      clock-names = "ref_clk";

      syscon = <&slcr>;

    };