Commit b14e889c authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Rob Herring
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dt-bindings: rtc: zynqmp: convert bindings to YAML 



Convert Real Time Clock for Xilinx Zynq MPSoC SoC bindings documentation
to YAML schemas.
And this renamed the file to compatible string of DT.

Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Link: https://lore.kernel.org/r/20210613205022.292575-1-iwamatsu@nigauri.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent b7705ba6

Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock



description:

  RTC controller for the Xilinx Zynq MPSoC Real Time Clock.

  The RTC controller has separate IRQ lines for seconds and alarm.



maintainers:

  - Michal Simek <michal.simek@xilinx.com>



allOf:

  - $ref: rtc.yaml#



properties:

  compatible:

    const: xlnx,zynqmp-rtc



  reg:

    maxItems: 1



  interrupts:

    minItems: 2



  interrupt-names:

    items:

      - const: alarm

      - const: sec



  calibration:

    description: |

      calibration value for 1 sec period which will

      be programmed directly to calibration register.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0x1

    maximum: 0x1FFFFF

    default: 0x198233



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names



additionalProperties: false



examples:

  - |

    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      rtc: rtc@ffa60000 {

        compatible = "xlnx,zynqmp-rtc";

        reg = <0x0 0xffa60000 0x0 0x100>;

        interrupt-parent = <&gic>;

        interrupts = <0 26 4>, <0 27 4>;

        interrupt-names = "alarm", "sec";

        calibration = <0x198233>;

      };

    };

Documentation/devicetree/bindings/rtc/xlnx-rtc.txt

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* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock



RTC controller for the Xilinx Zynq MPSoC Real Time Clock

Separate IRQ lines for seconds and alarm



Required properties:

- compatible: Should be "xlnx,zynqmp-rtc"

- reg: Physical base address of the controller and length

       of memory mapped region.

- interrupts: IRQ lines for the RTC.

- interrupt-names: interrupt line names eg. "sec" "alarm"



Optional:

- calibration: calibration value for 1 sec period which will

		be programmed directly to calibration register



Example:

rtc: rtc@ffa60000 {

	compatible = "xlnx,zynqmp-rtc";

	reg = <0x0 0xffa60000 0x100>;

	interrupt-parent = <&gic>;

	interrupts = <0 26 4>, <0 27 4>;

	interrupt-names = "alarm", "sec";

	calibration = <0x198233>;

};