!4048 [OLK-5.10] Intel: Backport PEBS format 5 support to OLK-5.10 for GNR/SRF Timed PEBS enabling

Merge Pull Request from: @yunyingsun 
 
Title: Intel: Backport PEBS format 5 support to OLK-5.10 for GNR/SRF Timed PEBS enabling

Content:
To support the new feature "Timed PEBS" which will be supported since next Intel Xeon platforms Granite Rapids(GNR) and Sierra Forest(SRF), PEBS format 5 is a pre-requisite.

PEBS format 5 support has been included in mainline kernel since kernel v5.18-rc1:
ee28855a perf/x86/intel: Increase max number of the fixed counters
0144ba0c KVM: x86: use the KVM side max supported fixed counter
2145e77f perf/x86/intel: Enable PEBS format 5

LKML: https://lore.kernel.org/lkml/1643750603-100733-1-git-send-email-kan.liang@linux.intel.com/

Since the Timed PEBS kernel commit:
(v6.3-rc1) c87a3109 perf/x86: Support Retire Latency
has been included and merged along with the SRF core PMU PR:
https://gitee.com/openeuler/kernel/pulls/3689

and besides that we won't backport the Timed PEBS needed user space perf tool patches(to avoid introducing too many dependencies):
4e846311 perf script: Fix missing Retire Latency fields option documentation
957ed139 perf event x86: Add retire_lat when synthesizing PERF_SAMPLE_WEIGHT_STRUCT
e65f91b2 perf test x86: Support the retire_lat (Retire Latency) sample_type check
17f248aa perf script: Support Retire Latency
d7d213e0 perf report: Support Retire Latency

so patches for enabling PEBS format 5 are all that needed for Timed PEBS support on OLK-5.10.

Note 1: one dependent commit has been identified:
(v5.14-rc1) 4c58d922 perf/x86/intel: Fix PEBS-via-PT reload base value for Extended PEBS
which is needed by (2145e77f perf/x86/intel: Enable PEBS format 5).

Note 2: this PR dependent on https://gitee.com/openeuler/kernel/pulls/3689.

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/I8WXIM

Test:
We've verified on Intel internal GNR/SRF platforms that both PEBS and timed PEBS work fine with this PR.

1. PEBS format
Without this PR, on GNR/SRF, with (# dmesg | grep -i "performance events") it returns:
[ 0.557984] Performance Events: XSAVE Architectural LBR, no PEBS fmt5+ , AnyThread deprecated, Crestmont events, 32-deep LBR, full-width counters, Intel PMU driver.
With this PR, on GNR/SRF, with (# dmesg | grep -i "performance events) it returns:
[ 0.611077] Performance Events: XSAVE Architectural LBR, PEBS fmt4+-baseline, PEBS-via-PT , AnyThread deprecated, Crestmont events, 32-deep LBR, full-width counters, Intel PMU driver.

2. Timed PEBS
Without this PR, on GNR/SRF there's no "mem-loads"/"mem-stores" event available with "perf list".
With this PR, on GNR/SRF:
a. "mem-loads"/"mem-stores" events are available with "perf list".
b. Timed PEBS works as there's non-zero data at the last(third) column in output of second command:
`# perf record -e cpu/mem-loads,ldlat=3/P --weight -d`
`# perf report -D -i perf.data | grep weight`

Known issue:
N/A

Default config change:
N/A 
 
Link:https://gitee.com/openeuler/kernel/pulls/4048

 

Reviewed-by: Xu Kuohai <xukuohai@huawei.com>
Reviewed-by: Jason Zeng <jason.zeng@intel.com>
Reviewed-by: Aichun Shi <aichun.shi@intel.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>