Commit 1d831cad authored by Amit Kumar Mahapatra's avatar Amit Kumar Mahapatra Committed by Michal Simek
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arm64: zynqmp: Set qspi tx-buswidth to 4 



All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller is capable of handling 1-4-4 write commands, so updated
the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the
tx data will be transferred on four lines instead on single line.

Signed-off-by: default avatarAmit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
parent f8673fd5

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts

+1 −1
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0>;

		spi-tx-bus-width = <1>;

		spi-tx-bus-width = <4>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <40000000>; /* 40MHz */

		partition@0 {

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-tx-bus-width = <4>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-tx-bus-width = <4>;

		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

+1 −1
Original line number Diff line number Diff line
@@ -355,7 +355,7 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-tx-bus-width = <4>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts

+1 −1
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-tx-bus-width = <4>;

		spi-rx-bus-width = <4>; /* also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};