Commit 1d66764d authored by Sandipan Das's avatar Sandipan Das Committed by Wenkuan Wang
Browse files

perf vendor events amd: Fix Zen 4 cache latency events 

mainline inclusion
from mainline-v6.9-rc1
commit 498d3486376befe4e82b5334d44bbc86b1982ee4
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9A3IS


CVE: NA

--------------------------------

L3PMCx0AC and L3PMCx0AD, used in l3_xi_sampled_latency* events, have a
quirk that requires them to be programmed with SliceId set to 0x3.
Without this, the events do not count at all and affects dependent
metrics such as l3_read_miss_latency.

If ThreadMask is not specified, the amd-uncore driver internally sets
ThreadMask to 0x3, EnAllCores to 0x1 and EnAllSlices to 0x1 but does
not set SliceId. Since SliceId must also be set to 0x3 in this case,
specify all the other fields explicitly.

E.g.

  $ sudo perf stat -e l3_xi_sampled_latency.all,l3_xi_sampled_latency_requests.all -a sleep 1

Before:

   Performance counter stats for 'system wide':

                   0      l3_xi_sampled_latency.all
                   0      l3_xi_sampled_latency_requests.all

         1.005155399 seconds time elapsed

After:

   Performance counter stats for 'system wide':

             921,446      l3_xi_sampled_latency.all
              54,210      l3_xi_sampled_latency_requests.all

         1.005664472 seconds time elapsed

Fixes: 5b2ca349 ("perf vendor events amd: Add Zen 4 uncore events")
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Cc: ananth.narayan@amd.com
Cc: ravi.bangoria@amd.com
Cc: eranian@google.com
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240301084431.646221-1-sandipan.das@amd.com


Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent be457264

tools/perf/pmu-events/arch/x86/amdzen4/cache.json

+56 −0
Original line number Diff line number Diff line
@@ -676,6 +676,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -683,6 +687,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -690,6 +698,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -697,6 +709,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -704,6 +720,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -711,6 +731,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -718,6 +742,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -725,6 +753,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -732,6 +764,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -739,6 +775,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -746,6 +786,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -753,6 +797,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -760,6 +808,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -767,6 +819,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  }

]

tools/perf/pmu-events/jevents.py

+4 −0
Original line number Diff line number Diff line
@@ -347,6 +347,10 @@ class JsonEvent: 
        ('SampleAfterValue', 'period='),

        ('UMask', 'umask='),

        ('RdWrMask', 'rdwrmask='),

        ('EnAllCores', 'enallcores='),

        ('EnAllSlices', 'enallslices='),

        ('SliceId', 'sliceid='),

        ('ThreadMask', 'threadmask='),

    ]

    for key, value in event_fields:

      if key in jd and jd[key] != '0':