Commit 1d47ae27 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "A typo fix for a PMU driver, a workround for a side-channel erratum on
  Cortex-A520 and a fix for the local timer save/restore when using ACPI
  with Qualcomm's custom CPUs:

   - Workaround for Cortex-A520 erratum #2966298

   - Fix typo in Arm CMN PMU driver that breaks counter overflow handling

   - Fix timer handling across idle for Qualcomm custom CPUs"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  cpuidle, ACPI: Evaluate LPI arch_flags for broadcast timer
  arm64: errata: Add Cortex-A520 speculative unprivileged load workaround
  arm64: Add Cortex-A520 CPU part definition
  perf/arm-cmn: Fix the unhandled overflow status of counter 4 to 7
parents 4940c154 4785aa80

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2658417        | ARM64_ERRATUM_2658417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A520     | #2966298        | ARM64_ERRATUM_2966298       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

arch/arm64/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -1037,6 +1037,19 @@ config ARM64_ERRATUM_2645198 


	  If unsure, say Y.



config ARM64_ERRATUM_2966298

	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"

	default y

	help

	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.



	  On an affected Cortex-A520 core, a speculatively executed unprivileged

	  load might leak data from a privileged level via a cache side channel.



	  Work around this problem by executing a TLBI before returning to EL0.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/acpi.h

+19 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#ifndef _ASM_ACPI_H

#define _ASM_ACPI_H



#include <linux/cpuidle.h>

#include <linux/efi.h>

#include <linux/memblock.h>

#include <linux/psci.h>
@@ -44,6 +45,24 @@ 


#define ACPI_MADT_GICC_TRBE  (offsetof(struct acpi_madt_generic_interrupt, \

	trbe_interrupt) + sizeof(u16))

/*

 * Arm® Functional Fixed Hardware Specification Version 1.2.

 * Table 2: Arm Architecture context loss flags

 */

#define CPUIDLE_CORE_CTXT		BIT(0) /* Core context Lost */



static inline unsigned int arch_get_idle_state_flags(u32 arch_flags)

{

	if (arch_flags & CPUIDLE_CORE_CTXT)

		return CPUIDLE_FLAG_TIMER_STOP;



	return 0;

}

#define arch_get_idle_state_flags arch_get_idle_state_flags



#define CPUIDLE_TRACE_CTXT		BIT(1) /* Trace context loss */

#define CPUIDLE_GICR_CTXT		BIT(2) /* GICR */

#define CPUIDLE_GICD_CTXT		BIT(3) /* GICD */



/* Basic configuration for ACPI */

#ifdef	CONFIG_ACPI

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 
#define ARM_CPU_PART_CORTEX_A78AE	0xD42

#define ARM_CPU_PART_CORTEX_X1		0xD44

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_A520	0xD80

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_A715	0xD4D

#define ARM_CPU_PART_CORTEX_X2		0xD48
@@ -148,6 +149,7 @@ 
#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)

#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)

#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

arch/arm64/kernel/cpu_errata.c

+8 −0
Original line number Diff line number Diff line
@@ -730,6 +730,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.cpu_enable = cpu_clear_bf16_from_user_emulation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2966298

	{

		.desc = "ARM erratum 2966298",

		.capability = ARM64_WORKAROUND_2966298,

		/* Cortex-A520 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),

	},

#endif

#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38

	{

		.desc = "AmpereOne erratum AC03_CPU_38",