Commit 1c405ca1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'mediatek-drm-next-5.17' of... 

Merge tag 'mediatek-drm-next-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux

 into drm-next

Mediatek DRM Next for Linux 5.16

1. Add support for MT8192
2. CMDQ refinement.
3. Miscellaneous clean up and reorder.
4. Set the default value of rotation to DRM_MODE_ROTATE_0

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1639700370-3541-1-git-send-email-chunkuang.hu@kernel.org
parents 8b70b5fe d95b00f1

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

+6 −0
Original line number Diff line number Diff line
@@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { 
	.matrix_bits = 10,

};



static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {

	.matrix_bits = 11,

};



static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {

	{ .compatible = "mediatek,mt8183-disp-ccorr",

	  .data = &mt8183_ccorr_driver_data},

	{ .compatible = "mediatek,mt8192-disp-ccorr",

	  .data = &mt8192_ccorr_driver_data},

	{},

};

MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

+20 −0
Original line number Diff line number Diff line
@@ -456,6 +456,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { 
	.fmt_rgb565_is_0 = true,

};



static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {

	.addr = DISP_REG_OVL_ADDR_MT8173,

	.gmc_bits = 10,

	.layer_nr = 4,

	.fmt_rgb565_is_0 = true,

	.smi_id_en = true,

};



static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {

	.addr = DISP_REG_OVL_ADDR_MT8173,

	.gmc_bits = 10,

	.layer_nr = 2,

	.fmt_rgb565_is_0 = true,

	.smi_id_en = true,

};



static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {

	{ .compatible = "mediatek,mt2701-disp-ovl",

	  .data = &mt2701_ovl_driver_data},
@@ -465,6 +481,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 
	  .data = &mt8183_ovl_driver_data},

	{ .compatible = "mediatek,mt8183-disp-ovl-2l",

	  .data = &mt8183_ovl_2l_driver_data},

	{ .compatible = "mediatek,mt8192-disp-ovl",

	  .data = &mt8192_ovl_driver_data},

	{ .compatible = "mediatek,mt8192-disp-ovl-2l",

	  .data = &mt8192_ovl_2l_driver_data},

	{},

};

MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

+6 −0
Original line number Diff line number Diff line
@@ -353,6 +353,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { 
	.fifo_size = 5 * SZ_1K,

};



static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {

	.fifo_size = 5 * SZ_1K,

};



static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {

	{ .compatible = "mediatek,mt2701-disp-rdma",

	  .data = &mt2701_rdma_driver_data},
@@ -360,6 +364,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { 
	  .data = &mt8173_rdma_driver_data},

	{ .compatible = "mediatek,mt8183-disp-rdma",

	  .data = &mt8183_rdma_driver_data},

	{ .compatible = "mediatek,mt8192-disp-rdma",

	  .data = &mt8192_rdma_driver_data},

	{},

};

MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);

drivers/gpu/drm/mediatek/mtk_drm_crtc.c

+151 −24
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
 */



#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/mailbox_controller.h>

#include <linux/pm_runtime.h>

#include <linux/soc/mediatek/mtk-cmdq.h>

#include <linux/soc/mediatek/mtk-mmsys.h>
@@ -50,8 +52,10 @@ struct mtk_drm_crtc { 
	bool				pending_async_planes;



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	struct cmdq_client		*cmdq_client;

	struct cmdq_client		cmdq_client;

	struct cmdq_pkt			cmdq_handle;

	u32				cmdq_event;

	u32				cmdq_vblank_cnt;

#endif



	struct device			*mmsys_dev;
@@ -104,12 +108,60 @@ static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 
	}

}



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,

				   size_t size)

{

	struct device *dev;

	dma_addr_t dma_addr;



	pkt->va_base = kzalloc(size, GFP_KERNEL);

	if (!pkt->va_base) {

		kfree(pkt);

		return -ENOMEM;

	}

	pkt->buf_size = size;

	pkt->cl = (void *)client;



	dev = client->chan->mbox->dev;

	dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,

				  DMA_TO_DEVICE);

	if (dma_mapping_error(dev, dma_addr)) {

		dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);

		kfree(pkt->va_base);

		kfree(pkt);

		return -ENOMEM;

	}



	pkt->pa_base = dma_addr;



	return 0;

}



static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)

{

	struct cmdq_client *client = (struct cmdq_client *)pkt->cl;



	dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,

			 DMA_TO_DEVICE);

	kfree(pkt->va_base);

	kfree(pkt);

}

#endif



static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);



	mtk_mutex_put(mtk_crtc->mutex);

#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);



	if (mtk_crtc->cmdq_client.chan) {

		mbox_free_channel(mtk_crtc->cmdq_client.chan);

		mtk_crtc->cmdq_client.chan = NULL;

	}

#endif

	drm_crtc_cleanup(crtc);

}
@@ -222,9 +274,46 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 
}



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

static void ddp_cmdq_cb(struct cmdq_cb_data data)

static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)

{

	cmdq_pkt_destroy(data.data);

	struct cmdq_cb_data *data = mssg;

	struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);

	struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client);

	struct mtk_crtc_state *state;

	unsigned int i;



	if (data->sta < 0)

		return;



	state = to_mtk_crtc_state(mtk_crtc->base.state);



	state->pending_config = false;



	if (mtk_crtc->pending_planes) {

		for (i = 0; i < mtk_crtc->layer_nr; i++) {

			struct drm_plane *plane = &mtk_crtc->planes[i];

			struct mtk_plane_state *plane_state;



			plane_state = to_mtk_plane_state(plane->state);



			plane_state->pending.config = false;

		}

		mtk_crtc->pending_planes = false;

	}



	if (mtk_crtc->pending_async_planes) {

		for (i = 0; i < mtk_crtc->layer_nr; i++) {

			struct drm_plane *plane = &mtk_crtc->planes[i];

			struct mtk_plane_state *plane_state;



			plane_state = to_mtk_plane_state(plane->state);



			plane_state->pending.async_config = false;

		}

		mtk_crtc->pending_async_planes = false;

	}



	mtk_crtc->cmdq_vblank_cnt = 0;

}

#endif
@@ -378,6 +467,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 
				    state->pending_vrefresh, 0,

				    cmdq_handle);



		if (!cmdq_handle)

			state->pending_config = false;

	}
@@ -398,8 +488,11 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 
				mtk_ddp_comp_layer_config(comp, local_layer,

							  plane_state,

							  cmdq_handle);

			if (!cmdq_handle)

				plane_state->pending.config = false;

		}



		if (!cmdq_handle)

			mtk_crtc->pending_planes = false;

	}
@@ -420,8 +513,11 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 
				mtk_ddp_comp_layer_config(comp, local_layer,

							  plane_state,

							  cmdq_handle);

			if (!cmdq_handle)

				plane_state->pending.async_config = false;

		}



		if (!cmdq_handle)

			mtk_crtc->pending_async_planes = false;

	}

}
@@ -430,7 +526,7 @@ static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 
				       bool needs_vblank)

{

#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	struct cmdq_pkt *cmdq_handle;

	struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;

#endif

	struct drm_crtc *crtc = &mtk_crtc->base;

	struct mtk_drm_private *priv = crtc->dev->dev_private;
@@ -468,14 +564,28 @@ static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 
		mtk_mutex_release(mtk_crtc->mutex);

	}

#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	if (mtk_crtc->cmdq_client) {

		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);

		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);

	if (mtk_crtc->cmdq_client.chan) {

		mbox_flush(mtk_crtc->cmdq_client.chan, 2000);

		cmdq_handle->cmd_buf_size = 0;

		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);

		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);

		mtk_crtc_ddp_config(crtc, cmdq_handle);

		cmdq_pkt_finalize(cmdq_handle);

		cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);

		dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,

					   cmdq_handle->pa_base,

					   cmdq_handle->cmd_buf_size,

					   DMA_TO_DEVICE);

		/*

		 * CMDQ command should execute in next 3 vblank.

		 * One vblank interrupt before send message (occasionally)

		 * and one vblank interrupt after cmdq done,

		 * so it's timeout after 3 vblank interrupt.

		 * If it fail to execute in next 3 vblank, timeout happen.

		 */

		mtk_crtc->cmdq_vblank_cnt = 3;



		mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);

		mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);

	}

#endif

	mtk_crtc->config_updating = false;
@@ -489,12 +599,15 @@ static void mtk_crtc_ddp_irq(void *data) 
	struct mtk_drm_private *priv = crtc->dev->dev_private;



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)

	if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)

		mtk_crtc_ddp_config(crtc, NULL);

	else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)

		DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",

			  drm_crtc_index(&mtk_crtc->base));

#else

	if (!priv->data->shadow_register)

#endif

		mtk_crtc_ddp_config(crtc, NULL);



#endif

	mtk_drm_finish_page_flip(mtk_crtc);

}
@@ -829,16 +942,20 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
	mutex_init(&mtk_crtc->hw_lock);



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	mtk_crtc->cmdq_client =

			cmdq_mbox_create(mtk_crtc->mmsys_dev,

	mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;

	mtk_crtc->cmdq_client.client.tx_block = false;

	mtk_crtc->cmdq_client.client.knows_txdone = true;

	mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;

	mtk_crtc->cmdq_client.chan =

			mbox_request_channel(&mtk_crtc->cmdq_client.client,

					     drm_crtc_index(&mtk_crtc->base));

	if (IS_ERR(mtk_crtc->cmdq_client)) {

	if (IS_ERR(mtk_crtc->cmdq_client.chan)) {

		dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",

			drm_crtc_index(&mtk_crtc->base));

		mtk_crtc->cmdq_client = NULL;

		mtk_crtc->cmdq_client.chan = NULL;

	}



	if (mtk_crtc->cmdq_client) {

	if (mtk_crtc->cmdq_client.chan) {

		ret = of_property_read_u32_index(priv->mutex_node,

						 "mediatek,gce-events",

						 drm_crtc_index(&mtk_crtc->base),
@@ -846,8 +963,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
		if (ret) {

			dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",

				drm_crtc_index(&mtk_crtc->base));

			cmdq_mbox_destroy(mtk_crtc->cmdq_client);

			mtk_crtc->cmdq_client = NULL;

			mbox_free_channel(mtk_crtc->cmdq_client.chan);

			mtk_crtc->cmdq_client.chan = NULL;

		} else {

			ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,

						      &mtk_crtc->cmdq_handle,

						      PAGE_SIZE);

			if (ret) {

				dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",

					drm_crtc_index(&mtk_crtc->base));

				mbox_free_channel(mtk_crtc->cmdq_client.chan);

				mtk_crtc->cmdq_client.chan = NULL;

			}

		}

	}

#endif

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

+125 −92
Original line number Diff line number Diff line
@@ -20,45 +20,39 @@ 
#include "mtk_drm_ddp_comp.h"

#include "mtk_drm_crtc.h"



#define DISP_OD_EN				0x0000

#define DISP_OD_INTEN				0x0008

#define DISP_OD_INTSTA				0x000c

#define DISP_OD_CFG				0x0020

#define DISP_OD_SIZE				0x0030

#define DISP_DITHER_5				0x0114

#define DISP_DITHER_7				0x011c

#define DISP_DITHER_15				0x013c

#define DISP_DITHER_16				0x0140



#define DISP_REG_UFO_START			0x0000



#define DISP_DITHER_EN				0x0000

#define DISP_REG_DITHER_EN			0x0000

#define DITHER_EN				BIT(0)

#define DISP_DITHER_CFG				0x0020

#define DISP_REG_DITHER_CFG			0x0020

#define DITHER_RELAY_MODE			BIT(0)

#define DITHER_ENGINE_EN			BIT(1)

#define DISP_DITHER_SIZE			0x0030



#define LUT_10BIT_MASK				0x03ff



#define OD_RELAYMODE				BIT(0)



#define UFO_BYPASS				BIT(2)



#define DISP_DITHERING				BIT(2)

#define DISP_REG_DITHER_SIZE			0x0030

#define DISP_REG_DITHER_5			0x0114

#define DISP_REG_DITHER_7			0x011c

#define DISP_REG_DITHER_15			0x013c

#define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)

#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)

#define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)

#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)

#define DITHER_NEW_BIT_MODE			BIT(0)

#define DISP_REG_DITHER_16			0x0140

#define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)

#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)

#define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)

#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)

#define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)

#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)

#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)

#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)



#define DISP_REG_OD_EN				0x0000

#define DISP_REG_OD_CFG				0x0020

#define OD_RELAYMODE				BIT(0)

#define DISP_REG_OD_SIZE			0x0030



#define DISP_REG_POSTMASK_EN			0x0000

#define POSTMASK_EN					BIT(0)

#define DISP_REG_POSTMASK_CFG			0x0020

#define POSTMASK_RELAY_MODE				BIT(0)

#define DISP_REG_POSTMASK_SIZE			0x0030



#define DISP_REG_UFO_START			0x0000

#define UFO_BYPASS				BIT(2)



struct mtk_ddp_comp_dev {

	struct clk *clk;
@@ -134,23 +128,50 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, 
		return;



	if (bpc >= MTK_MIN_BPC) {

		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);

		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);

		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);

		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);

		mtk_ddp_write(cmdq_pkt,

			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |

			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |

			      DITHER_NEW_BIT_MODE,

			      cmdq_reg, regs, DISP_DITHER_15);

			      cmdq_reg, regs, DISP_REG_DITHER_15);

		mtk_ddp_write(cmdq_pkt,

			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |

			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |

			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |

			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),

			      cmdq_reg, regs, DISP_DITHER_16);

			      cmdq_reg, regs, DISP_REG_DITHER_16);

		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);

	}

}



static void mtk_dither_config(struct device *dev, unsigned int w,

			      unsigned int h, unsigned int vrefresh,

			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);

	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,

		      DISP_REG_DITHER_CFG);

	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,

			      DITHER_ENGINE_EN, cmdq_pkt);

}



static void mtk_dither_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);

}



static void mtk_dither_stop(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);

}



static void mtk_dither_set(struct device *dev, unsigned int bpc,

			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)

{
@@ -166,49 +187,49 @@ static void mtk_od_config(struct device *dev, unsigned int w, 
{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);

	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);

	mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);

	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);

	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);

	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);

}



static void mtk_od_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(1, priv->regs + DISP_OD_EN);

	writel(1, priv->regs + DISP_REG_OD_EN);

}



static void mtk_ufoe_start(struct device *dev)

static void mtk_postmask_config(struct device *dev, unsigned int w,

				unsigned int h, unsigned int vrefresh,

				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);

	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,

		      DISP_REG_POSTMASK_SIZE);

	mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,

		      priv->regs, DISP_REG_POSTMASK_CFG);

}



static void mtk_dither_config(struct device *dev, unsigned int w,

			      unsigned int h, unsigned int vrefresh,

			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

static void mtk_postmask_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);

	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);

	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,

			      DITHER_ENGINE_EN, cmdq_pkt);

	writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);

}



static void mtk_dither_start(struct device *dev)

static void mtk_postmask_stop(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(DITHER_EN, priv->regs + DISP_DITHER_EN);

	writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);

}



static void mtk_dither_stop(struct device *dev)

static void mtk_ufoe_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);

	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);

}



static const struct mtk_ddp_comp_funcs ddp_aal = {
@@ -286,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { 
	.bgclr_in_off = mtk_ovl_bgclr_in_off,

};



static const struct mtk_ddp_comp_funcs ddp_postmask = {

	.clk_enable = mtk_ddp_clk_enable,

	.clk_disable = mtk_ddp_clk_disable,

	.config = mtk_postmask_config,

	.start = mtk_postmask_start,

	.stop = mtk_postmask_stop,

};



static const struct mtk_ddp_comp_funcs ddp_rdma = {

	.clk_enable = mtk_rdma_clk_enable,

	.clk_disable = mtk_rdma_clk_disable,
@@ -305,22 +334,23 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = { 
};



static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {

	[MTK_DISP_AAL] = "aal",

	[MTK_DISP_BLS] = "bls",

	[MTK_DISP_CCORR] = "ccorr",

	[MTK_DISP_COLOR] = "color",

	[MTK_DISP_DITHER] = "dither",

	[MTK_DISP_GAMMA] = "gamma",

	[MTK_DISP_MUTEX] = "mutex",

	[MTK_DISP_OD] = "od",

	[MTK_DISP_OVL] = "ovl",

	[MTK_DISP_OVL_2L] = "ovl-2l",

	[MTK_DISP_POSTMASK] = "postmask",

	[MTK_DISP_PWM] = "pwm",

	[MTK_DISP_RDMA] = "rdma",

	[MTK_DISP_WDMA] = "wdma",

	[MTK_DISP_COLOR] = "color",

	[MTK_DISP_CCORR] = "ccorr",

	[MTK_DISP_AAL] = "aal",

	[MTK_DISP_GAMMA] = "gamma",

	[MTK_DISP_DITHER] = "dither",

	[MTK_DISP_UFOE] = "ufoe",

	[MTK_DSI] = "dsi",

	[MTK_DISP_WDMA] = "wdma",

	[MTK_DPI] = "dpi",

	[MTK_DISP_PWM] = "pwm",

	[MTK_DISP_MUTEX] = "mutex",

	[MTK_DISP_OD] = "od",

	[MTK_DISP_BLS] = "bls",

	[MTK_DSI] = "dsi",

};



struct mtk_ddp_comp_match {
@@ -350,12 +380,15 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 
	[DDP_COMPONENT_OVL1]		= { MTK_DISP_OVL,	1, &ddp_ovl },

	[DDP_COMPONENT_OVL_2L0]		= { MTK_DISP_OVL_2L,	0, &ddp_ovl },

	[DDP_COMPONENT_OVL_2L1]		= { MTK_DISP_OVL_2L,	1, &ddp_ovl },

	[DDP_COMPONENT_OVL_2L2]		= { MTK_DISP_OVL_2L,    2, &ddp_ovl },

	[DDP_COMPONENT_POSTMASK0]	= { MTK_DISP_POSTMASK,	0, &ddp_postmask },

	[DDP_COMPONENT_PWM0]		= { MTK_DISP_PWM,	0, NULL },

	[DDP_COMPONENT_PWM1]		= { MTK_DISP_PWM,	1, NULL },

	[DDP_COMPONENT_PWM2]		= { MTK_DISP_PWM,	2, NULL },

	[DDP_COMPONENT_RDMA0]		= { MTK_DISP_RDMA,	0, &ddp_rdma },

	[DDP_COMPONENT_RDMA1]		= { MTK_DISP_RDMA,	1, &ddp_rdma },

	[DDP_COMPONENT_RDMA2]		= { MTK_DISP_RDMA,	2, &ddp_rdma },

	[DDP_COMPONENT_RDMA4]		= { MTK_DISP_RDMA,      4, &ddp_rdma },

	[DDP_COMPONENT_UFOE]		= { MTK_DISP_UFOE,	0, &ddp_ufoe },

	[DDP_COMPONENT_WDMA0]		= { MTK_DISP_WDMA,	0, NULL },

	[DDP_COMPONENT_WDMA1]		= { MTK_DISP_WDMA,	1, NULL },
@@ -475,12 +508,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, 
	    type == MTK_DISP_CCORR ||

	    type == MTK_DISP_COLOR ||

	    type == MTK_DISP_GAMMA ||

	    type == MTK_DPI ||

	    type == MTK_DSI ||

	    type == MTK_DISP_OVL ||

	    type == MTK_DISP_OVL_2L ||

	    type == MTK_DISP_PWM ||

	    type == MTK_DISP_RDMA)

	    type == MTK_DISP_RDMA ||

	    type == MTK_DPI ||

	    type == MTK_DSI)

		return 0;



	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);