Unverified Commit 1b4212c6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!5412 [OLK-6.6] perf/x86/amd: Miscellaneous fixes 

Merge Pull Request from: @kile2009 
 
backporting the bugfix from upstream kernel version 6.9 for AMD perf
https://lore.kernel.org/all/cover.1706526029.git.sandipan.das@amd.com/

ad8c91282c95f801c37812d59d2d9eba6899b384 v6.9-rc1 perf/x86/amd/core: Avoid register reset when CPU is dead
29297ffffb0bf388778bd4b581a43cee6929ae65 v6.9-rc1 perf/x86/amd/lbr: Discard erroneous branch entries
498d3486376befe4e82b5334d44bbc86b1982ee4 v6.9-rc1 perf vendor events amd: Fix Zen 4 cache latency events 
 
Link:https://gitee.com/openeuler/kernel/pulls/5412

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 0342dc44 1d66764d

arch/x86/events/amd/core.c

+0 −1
Original line number Diff line number Diff line
@@ -604,7 +604,6 @@ static void amd_pmu_cpu_dead(int cpu) 


	kfree(cpuhw->lbr_sel);

	cpuhw->lbr_sel = NULL;

	amd_pmu_cpu_reset(cpu);



	if (!x86_pmu.amd_nb_constraints)

		return;

arch/x86/events/amd/lbr.c

+4 −2
Original line number Diff line number Diff line
@@ -173,9 +173,11 @@ void amd_pmu_lbr_read(void) 


		/*

		 * Check if a branch has been logged; if valid = 0, spec = 0

		 * then no branch was recorded

		 * then no branch was recorded; if reserved = 1 then an

		 * erroneous branch was recorded (see Erratum 1452)

		 */

		if (!entry.to.split.valid && !entry.to.split.spec)

		if ((!entry.to.split.valid && !entry.to.split.spec) ||

		    entry.to.split.reserved)

			continue;



		perf_clear_branch_entry_bitfields(br + out);

tools/perf/pmu-events/arch/x86/amdzen4/cache.json

+56 −0
Original line number Diff line number Diff line
@@ -676,6 +676,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -683,6 +687,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -690,6 +698,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -697,6 +709,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -704,6 +720,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -711,6 +731,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -718,6 +742,10 @@ 
    "EventCode": "0xac",

    "BriefDescription": "Average sampled latency from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -725,6 +753,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",

    "UMask": "0x01",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -732,6 +764,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",

    "UMask": "0x02",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -739,6 +775,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",

    "UMask": "0x04",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -746,6 +786,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",

    "UMask": "0x08",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -753,6 +797,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",

    "UMask": "0x10",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -760,6 +808,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",

    "UMask": "0x20",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  },

  {
@@ -767,6 +819,10 @@ 
    "EventCode": "0xad",

    "BriefDescription": "L3 cache fill requests sourced from all data sources.",

    "UMask": "0x3f",

    "EnAllCores": "0x1",

    "EnAllSlices": "0x1",

    "SliceId": "0x3",

    "ThreadMask": "0x3",

    "Unit": "L3PMC"

  }

]

tools/perf/pmu-events/jevents.py

+4 −0
Original line number Diff line number Diff line
@@ -347,6 +347,10 @@ class JsonEvent: 
        ('SampleAfterValue', 'period='),

        ('UMask', 'umask='),

        ('RdWrMask', 'rdwrmask='),

        ('EnAllCores', 'enallcores='),

        ('EnAllSlices', 'enallslices='),

        ('SliceId', 'sliceid='),

        ('ThreadMask', 'threadmask='),

    ]

    for key, value in event_fields:

      if key in jd and jd[key] != '0':