Unverified Commit 1a5a2cbd authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Use composable cache instead of L2 cache" 

Zong Li <zong.li@sifive.com> says:

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

* b4-shazam-merge:
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 6224db78 da29dbcd

Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml→Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml

+23 −5
Original line number Diff line number Diff line
@@ -2,18 +2,18 @@ 
# Copyright (C) 2020 SiFive, Inc.

%YAML 1.2

---

$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#

$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SiFive L2 Cache Controller

title: SiFive Composable Cache Controller



maintainers:

  - Sagar Kadam <sagar.kadam@sifive.com>

  - Paul Walmsley  <paul.walmsley@sifive.com>



description:

  The SiFive Level 2 Cache Controller is used to provide access to fast copies

  of memory for masters in a Core Complex. The Level 2 Cache Controller also

  The SiFive Composable Cache Controller is used to provide access to fast copies

  of memory for masters in a Core Complex. The Composable Cache Controller also

  acts as directory-based coherency manager.

  All the properties in ePAPR/DeviceTree specification applies for this platform.
@@ -22,6 +22,7 @@ select: 
    compatible:

      contains:

        enum:

          - sifive,ccache0

          - sifive,fu540-c000-ccache

          - sifive,fu740-c000-ccache
@@ -33,6 +34,7 @@ properties: 
    oneOf:

      - items:

          - enum:

              - sifive,ccache0

              - sifive,fu540-c000-ccache

              - sifive,fu740-c000-ccache

          - const: cache
@@ -45,7 +47,7 @@ properties: 
    const: 64



  cache-level:

    const: 2

    enum: [2, 3]



  cache-sets:

    enum: [1024, 2048]
@@ -115,6 +117,22 @@ allOf: 
        cache-sets:

          const: 1024



  - if:

      properties:

        compatible:

          contains:

            const: sifive,ccache0



    then:

      properties:

        cache-level:

          enum: [2, 3]



    else:

      properties:

        cache-level:

          const: 2



additionalProperties: false



required:

arch/riscv/include/asm/elf.h

+4 −0
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ do { \ 
		get_cache_size(2, CACHE_TYPE_UNIFIED));		\

	NEW_AUX_ENT(AT_L2_CACHEGEOMETRY,			\

		get_cache_geometry(2, CACHE_TYPE_UNIFIED));	\

	NEW_AUX_ENT(AT_L3_CACHESIZE,				\

		get_cache_size(3, CACHE_TYPE_UNIFIED));		\

	NEW_AUX_ENT(AT_L3_CACHEGEOMETRY,			\

		get_cache_geometry(3, CACHE_TYPE_UNIFIED));	\

} while (0)

#define ARCH_HAS_SETUP_ADDITIONAL_PAGES

struct linux_binprm;

arch/riscv/include/uapi/asm/auxvec.h

+3 −1
Original line number Diff line number Diff line
@@ -30,8 +30,10 @@ 
#define AT_L1D_CACHEGEOMETRY	43

#define AT_L2_CACHESIZE		44

#define AT_L2_CACHEGEOMETRY	45

#define AT_L3_CACHESIZE		46

#define AT_L3_CACHEGEOMETRY	47



/* entries in ARCH_DLINFO */

#define AT_VECTOR_SIZE_ARCH	7

#define AT_VECTOR_SIZE_ARCH	9



#endif /* _UAPI_ASM_RISCV_AUXVEC_H */

drivers/edac/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC 


config EDAC_SIFIVE

	bool "Sifive platform EDAC driver"

	depends on EDAC=y && SIFIVE_L2

	depends on EDAC=y && SIFIVE_CCACHE

	help

	  Support for error detection and correction on the SiFive SoCs.

drivers/edac/sifive_edac.c

+6 −6
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * SiFive Platform EDAC Driver

 *

 * Copyright (C) 2018-2019 SiFive, Inc.

 * Copyright (C) 2018-2022 SiFive, Inc.

 *

 * This driver is partially based on octeon_edac-pc.c

 *
@@ -10,7 +10,7 @@ 
#include <linux/edac.h>

#include <linux/platform_device.h>

#include "edac_module.h"

#include <soc/sifive/sifive_l2_cache.h>

#include <soc/sifive/sifive_ccache.h>



#define DRVNAME "sifive_edac"
@@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) 


	p = container_of(this, struct sifive_edac_priv, notifier);



	if (event == SIFIVE_L2_ERR_TYPE_UE)

	if (event == SIFIVE_CCACHE_ERR_TYPE_UE)

		edac_device_handle_ue(p->dci, 0, 0, msg);

	else if (event == SIFIVE_L2_ERR_TYPE_CE)

	else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)

		edac_device_handle_ce(p->dci, 0, 0, msg);



	return NOTIFY_OK;
@@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) 
		goto err;

	}



	register_sifive_l2_error_notifier(&p->notifier);

	register_sifive_ccache_error_notifier(&p->notifier);



	return 0;
@@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) 
{

	struct sifive_edac_priv *p = platform_get_drvdata(pdev);



	unregister_sifive_l2_error_notifier(&p->notifier);

	unregister_sifive_ccache_error_notifier(&p->notifier);

	edac_device_del_device(&pdev->dev);

	edac_device_free_ctl_info(p->dci);