Unverified Commit 6224db78 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Some style cleanups for recent extension additions" 

Heiko Stuebner <heiko@sntech.de> says:

As noted by some people, some parts of the recently added extensions
(svpbmt, zicbom) + t-head errata could use some styling upgrades.

So this series provides these.

changes in v2:
- add patch also converting cpufeature probe to BIT()
- update commit message in patch1 (Conor)

Heiko Stuebner (5):
  riscv: cleanup svpbmt cpufeature probing
  riscv: drop some idefs from CMO initialization
  riscv: use BIT() macros in t-head errata init
  riscv: use BIT() marco for cpufeature probing
  riscv: check for kernel config option in t-head memory types errata

arch/riscv/errata/thead/errata.c    | 14 ++++++-----
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/kernel/cpufeature.c      | 39 ++++++++++++-----------------
 3 files changed, 26 insertions(+), 29 deletions(-)

Link: https://lore.kernel.org/r/20220905111027.2463297-1-heiko@sntech.de



* b4-shazam-merge:
  riscv: check for kernel config option in t-head memory types errata
  riscv: use BIT() marco for cpufeature probing
  riscv: use BIT() macros in t-head errata init
  riscv: drop some idefs from CMO initialization
  riscv: cleanup svpbmt cpufeature probing

Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 3cebf80e 14057733

arch/riscv/errata/thead/errata.c

+8 −6
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
static bool errata_probe_pbmt(unsigned int stage,

			      unsigned long arch_id, unsigned long impid)

{

	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))

		return false;



	if (arch_id != 0 || impid != 0)

		return false;
@@ -30,7 +33,9 @@ static bool errata_probe_pbmt(unsigned int stage, 
static bool errata_probe_cmo(unsigned int stage,

			     unsigned long arch_id, unsigned long impid)

{

#ifdef CONFIG_ERRATA_THEAD_CMO

	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))

		return false;



	if (arch_id != 0 || impid != 0)

		return false;
@@ -40,9 +45,6 @@ static bool errata_probe_cmo(unsigned int stage, 
	riscv_cbom_block_size = L1_CACHE_BYTES;

	riscv_noncoherent_supported();

	return true;

#else

	return false;

#endif

}



static u32 thead_errata_probe(unsigned int stage,
@@ -51,10 +53,10 @@ static u32 thead_errata_probe(unsigned int stage, 
	u32 cpu_req_errata = 0;



	if (errata_probe_pbmt(stage, archid, impid))

		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);

		cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);



	if (errata_probe_cmo(stage, archid, impid))

		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);

		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);



	return cpu_req_errata;

}

arch/riscv/include/asm/cacheflush.h

+2 −0
Original line number Diff line number Diff line
@@ -55,6 +55,8 @@ static inline void riscv_init_cbom_blocksize(void) { } 


#ifdef CONFIG_RISCV_DMA_NONCOHERENT

void riscv_noncoherent_supported(void);

#else

static inline void riscv_noncoherent_supported(void) {}

#endif



/*

arch/riscv/kernel/cpufeature.c

+16 −23
Original line number Diff line number Diff line
@@ -253,35 +253,28 @@ void __init riscv_fill_hwcap(void) 
#ifdef CONFIG_RISCV_ALTERNATIVE

static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)

{

#ifdef CONFIG_RISCV_ISA_SVPBMT

	switch (stage) {

	case RISCV_ALTERNATIVES_EARLY_BOOT:

	if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))

		return false;

	default:

		return riscv_isa_extension_available(NULL, SVPBMT);

	}

#endif



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;



	return riscv_isa_extension_available(NULL, SVPBMT);

}



static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)

{

#ifdef CONFIG_RISCV_ISA_ZICBOM

	switch (stage) {

	case RISCV_ALTERNATIVES_EARLY_BOOT:

	if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))

		return false;

	default:

		if (riscv_isa_extension_available(NULL, ZICBOM)) {

			riscv_noncoherent_supported();

			return true;

		} else {



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;

		}

	}

#endif



	if (!riscv_isa_extension_available(NULL, ZICBOM))

		return false;



	riscv_noncoherent_supported();

	return true;

}



/*
@@ -296,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage) 
	u32 cpu_req_feature = 0;



	if (cpufeature_probe_svpbmt(stage))

		cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);

		cpu_req_feature |= BIT(CPUFEATURE_SVPBMT);



	if (cpufeature_probe_zicbom(stage))

		cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);

		cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);



	return cpu_req_feature;

}