arm64/fp: Make SVE and SME length register definition match architecture

mainline inclusion
from mainline-v5.19-rc1
commit f171f9e4
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8E73O
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f171f9e4097d29db88a99ea96bb6c08e819a52a4



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Currently (as of DDI0487H.a) the architecture defines the vector length
control field in ZCR and SMCR as being 4 bits wide with an additional 5
bits reserved above it marked as RAZ/WI for future expansion. The kernel
currently attempts to anticipate such expansion by treating these extra
bits as part of the LEN field but this will be inconvenient when we start
generating the defines and would cause problems in the event that the
architecture goes a different direction with these fields. Let's instead
change the defines to reflect the currently defined architecture, we can
update in future as needed.

No change in behaviour should be seen in any system, even emulated systems
using the maximum allowed vector length for the current architecture.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220510161208.631259-2-broonie@kernel.org


Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Wang ShaoBo <bobo.shaobowang@huawei.com>