Commit 18ef0827 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "This time around we have a smaller pull request than usual and this
  includes code removal, so should be good!

  New drivers/devices
   - Support for QCOM SM8250 GPI DMA
   - removal of shdma-of driver and binding

  Updates:
   - arm-pl08x yaml binding move
   - altera-msgdma gained DT support
   - removal of imx-sdma platform data support
   - idxd and xilinx driver updates"

* tag 'dmaengine-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (22 commits)
  dmaengine: imx-sdma: Remove platform data header
  dmaengine: xilinx: dpdma: Fix spacing around addr[i-1]
  dmaengine: xilinx: dpdma: Use kernel type u32 over uint32_t
  dmaengine: altera-msgdma: add OF support
  MAINTAINERS: add entry for Altera mSGDMA
  dt-bindings: dma: add schema for altera-msgdma
  dmaengine: xilinx: dpdma: fix kernel-doc
  dmaengine: sf-pdma: apply proper spinlock flags in sf_pdma_prep_dma_memcpy()
  dmaengine: sh: Remove unused shdma-of driver
  dt-bindings: dmaengine: Remove SHDMA Device Tree bindings
  dmaengine: qcom: gpi: Add SM8250 compatible
  dt-bindings: dmaengine: qcom: gpi: add compatible for sm8250
  dmaengine: sun4i: Use list_move_tail instead of list_del/list_add_tail
  dmaengine: ti: omap-dma: Skip pointless cpu_pm context restore on errors
  dmaengine: hsu: Account transferred bytes
  dmaengine: Move kdoc description of struct dma_chan_percpu closer to it
  dmaengine: xilinx: dpdma: Print debug message when losing vsync race
  dmaengine: xilinx: dpdma: Print channel number in kernel log messages
  dt-bindings: dma: convert arm-pl08x to yaml
  dmaengine: idxd: remove devm allocation for idxd->int_handles
  ...
parents 8f3f2ccf 8d11cfb0

Documentation/devicetree/bindings/dma/altr,msgdma.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Altera mSGDMA IP core



maintainers:

  - Olivier Dautricourt <olivier.dautricourt@orolia.com>



description: |

  Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)

  intellectual property (IP)



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    const: altr,socfpga-msgdma



  reg:

    items:

      - description: Control and Status Register Slave Port

      - description: Descriptor Slave Port

      - description: Response Slave Port



  reg-names:

    items:

      - const: csr

      - const: desc

      - const: resp



  interrupts:

    maxItems: 1



  "#dma-cells":

    const: 1

    description:

      The cell identifies the channel id (must be 0)



required:

  - compatible

  - reg

  - reg-names

  - interrupts



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    msgdma_controller: dma-controller@ff200b00 {

        compatible = "altr,socfpga-msgdma";

        reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;

        reg-names = "csr", "desc", "resp";

        interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;

        #dma-cells = <1>;

    };

Documentation/devicetree/bindings/dma/arm-pl08x.txt

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* ARM PrimeCells PL080 and PL081 and derivatives DMA controller



Required properties:

- compatible: "arm,pl080", "arm,primecell";

	      "arm,pl081", "arm,primecell";

	      "faraday,ftdmac020", "arm,primecell"

- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded

  in the hardware and must be specified here as <0x0003b080>. This number

  follows the PrimeCell standard numbering using the JEP106 vendor code 0x38

  for Faraday Technology.

- reg: Address range of the PL08x registers

- interrupt: The PL08x interrupt number

- clocks: The clock running the IP core clock

- clock-names: Must contain "apb_pclk"

- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs

- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs

- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents

- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents

- #dma-cells: must be <2>. First cell should contain the DMA request,

              second cell should contain either 1 or 2 depending on

              which AHB master that is used.



Optional properties:

- dma-channels: contains the total number of DMA channels supported by the DMAC

- dma-requests: contains the total number of DMA requests supported by the DMAC

- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32

  64, 128 or 256 bytes are legal values

- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal

  values, the Faraday FTDMAC020 can also accept 64 bits



Clients

Required properties:

- dmas: List of DMA controller phandle, request channel and AHB master id

- dma-names: Names of the aforementioned requested channels



Example:



dmac0: dma-controller@10130000 {

	compatible = "arm,pl080", "arm,primecell";

	reg = <0x10130000 0x1000>;

	interrupt-parent = <&vica>;

	interrupts = <15>;

	clocks = <&hclkdma0>;

	clock-names = "apb_pclk";

	lli-bus-interface-ahb1;

	lli-bus-interface-ahb2;

	mem-bus-interface-ahb2;

	memcpy-burst-size = <256>;

	memcpy-bus-width = <32>;

	#dma-cells = <2>;

};



device@40008000 {

	...

	dmas = <&dmac0 0 2

		&dmac0 1 2>;

	dma-names = "tx", "rx";

	...

};

Documentation/devicetree/bindings/dma/arm-pl08x.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller



maintainers:

  - Vinod Koul <vkoul@kernel.org>



allOf:

  - $ref: "dma-controller.yaml#"



# We need a select here so we don't match all nodes with 'arm,primecell'

select:

  properties:

    compatible:

      contains:

        enum:

          - arm,pl080

          - arm,pl081

  required:

    - compatible



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - arm,pl080

              - arm,pl081

          - const: arm,primecell

      - items:

          - const: faraday,ftdma020

          - const: arm,pl080

          - const: arm,primecell



  reg:

    maxItems: 1

    description: Address range of the PL08x registers



  interrupts:

    minItems: 1

    description: The PL08x interrupt number



  clocks:

    minItems: 1

    description: The clock running the IP core clock



  clock-names:

    maxItems: 1



  lli-bus-interface-ahb1:

    type: boolean

    description: if AHB master 1 is eligible for fetching LLIs



  lli-bus-interface-ahb2:

    type: boolean

    description: if AHB master 2 is eligible for fetching LLIs



  mem-bus-interface-ahb1:

    type: boolean

    description: if AHB master 1 is eligible for fetching memory contents



  mem-bus-interface-ahb2:

    type: boolean

    description: if AHB master 2 is eligible for fetching memory contents



  memcpy-burst-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum:

      - 1

      - 4

      - 8

      - 16

      - 32

      - 64

      - 128

      - 256

    description: the size of the bursts for memcpy



  memcpy-bus-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum:

      - 8

      - 16

      - 32

      - 64

    description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits



required:

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#dma-cells"



unevaluatedProperties: false



examples:

  - |

    dmac0: dma-controller@10130000 {

      compatible = "arm,pl080", "arm,primecell";

      reg = <0x10130000 0x1000>;

      interrupt-parent = <&vica>;

      interrupts = <15>;

      clocks = <&hclkdma0>;

      clock-names = "apb_pclk";

      lli-bus-interface-ahb1;

      lli-bus-interface-ahb2;

      mem-bus-interface-ahb2;

      memcpy-burst-size = <256>;

      memcpy-bus-width = <32>;

      #dma-cells = <2>;

    };

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/reset/cortina,gemini-reset.h>

    #include <dt-bindings/clock/cortina,gemini-clock.h>

    dma-controller@67000000 {

      compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";

      /* Faraday Technology FTDMAC020 variant */

      arm,primecell-periphid = <0x0003b080>;

      reg = <0x67000000 0x1000>;

      interrupts = <9 IRQ_TYPE_EDGE_RISING>;

      resets = <&syscon GEMINI_RESET_DMAC>;

      clocks = <&syscon GEMINI_CLK_AHB>;

      clock-names = "apb_pclk";

      /* Bus interface AHB1 (AHB0) is totally tilted */

      lli-bus-interface-ahb2;

      mem-bus-interface-ahb2;

      memcpy-burst-size = <256>;

      memcpy-bus-width = <32>;

      #dma-cells = <2>;

    };

Documentation/devicetree/bindings/dma/qcom,gpi.yaml

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@@ -21,6 +21,7 @@ properties: 
    enum:

      - qcom,sdm845-gpi-dma

      - qcom,sm8150-gpi-dma

      - qcom,sm8250-gpi-dma



  reg:

    maxItems: 1

Documentation/devicetree/bindings/dma/renesas,shdma.txt

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* SHDMA Device Tree bindings



Sh-/r-mobile and R-Car systems often have multiple identical DMA controller

instances, capable of serving any of a common set of DMA slave devices, using

the same configuration. To describe this topology we require all compatible

SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible

DMAC instances have the same number of channels and use the same DMA

descriptors. Therefore respective DMA DT bindings can also all be placed in the

multiplexer node. Even if there is only one such DMAC instance on a system, it

still has to be placed under such a multiplexer node.



* DMA multiplexer



Required properties:

- compatible:	should be "renesas,shdma-mux"

- #dma-cells:	should be <1>, see "dmas" property below



Optional properties (currently unused):

- dma-channels:	number of DMA channels

- dma-requests:	number of DMA request signals



* DMA controller



Required properties:

- compatible:	should be of the form "renesas,shdma-<soc>", where <soc> should

		be replaced with the desired SoC model, e.g.

		"renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC



Example:

	dmac: dma-multiplexer@0 {

		compatible = "renesas,shdma-mux";

		#dma-cells = <1>;

		dma-channels = <20>;

		dma-requests = <256>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		dma0: dma-controller@e6700020 {

			compatible = "renesas,shdma-r8a73a4";

			reg = <0 0xe6700020 0 0x89e0>;

			interrupt-parent = <&gic>;

			interrupts = <0 220 4

					0 200 4

					0 201 4

					0 202 4

					0 203 4

					0 204 4

					0 205 4

					0 206 4

					0 207 4

					0 208 4

					0 209 4

					0 210 4

					0 211 4

					0 212 4

					0 213 4

					0 214 4

					0 215 4

					0 216 4

					0 217 4

					0 218 4

					0 219 4>;

			interrupt-names = "error",

					"ch0", "ch1", "ch2", "ch3",

					"ch4", "ch5", "ch6", "ch7",

					"ch8", "ch9", "ch10", "ch11",

					"ch12", "ch13", "ch14", "ch15",

					"ch16", "ch17", "ch18", "ch19";

		};

	};



* DMA client



Required properties:

- dmas:		a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,

		where MID/RID values are fixed handles, specified in the SoC

		manual

- dma-names:	a list of DMA channel names, one per "dmas" entry



Example:

	dmas = <&dmac 0xd1

		&dmac 0xd2>;

	dma-names = "tx", "rx";