Commit 17bf3df9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-07-28' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular scheduled fixes, msm and amdgpu leading the way, with some
  i915 and a single misc fbdev, all seems fine.

  fbdev:
   - remove unused function

  amdgpu:
   - gfxhub partition fix
   - Fix error handling in psp_sw_init()
   - SMU13 fix
   - DCN 3.1 fix
   - DCN 3.2 fix
   - Fix for display PHY programming sequence
   - DP MST error handling fix
   - GFX 9.4.3 fix

  amdkfd:
   - GFX11 trap handling fix

  i915:
   - Use shmem for dpt objects
   - Fix an error handling path in igt_write_huge()

  msm:
   - display:
      - Fix to correct the UBWC programming for decoder version 4.3 seen
        on SM8550
      - Add the missing flush and fetch bits for DMA4 and DMA5 SSPPs.
      - Fix to drop the unused dpu_core_perf_data_bus_id enum from the
        code
      - Drop the unused dsi_phy_14nm_17mA_regulators from QCM 2290 DSI
        cfg.
   - gpu:
      - Fix warn splat for newer devices without revn
      - Remove name/revn for a690.. we shouldn't be populating these for
        newer devices, for consistency, but it slipped through review
      - Fix a6xx gpu snapshot BINDLESS_DATA size (was listed in bytes
        instead of dwords, causing AHB faults on a6xx gen4/a660-family)
      - Disallow submit with fence id 0"

* tag 'drm-fixes-2023-07-28' of git://anongit.freedesktop.org/drm/drm: (22 commits)
  drm/msm: Disallow submit with fence id 0
  drm/amdgpu: Restore HQD persistent state register
  drm/amd/display: Unlock on error path in dm_handle_mst_sideband_msg_ready_event()
  drm/amd/display: Exit idle optimizations before attempt to access PHY
  drm/amd/display: Don't apply FIFO resync W/A if rdivider = 0
  drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family
  drm/amd/smu: use AverageGfxclkFrequency* to replace previous GFX Curr Clock
  drm/amd: Fix an error handling mistake in psp_sw_init()
  drm/amdgpu: Fix infinite loop in gfxhub_v1_2_xcc_gart_enable (v2)
  drm/amdkfd: fix trap handling work around for debugging
  drm/fb-helper: Remove unused inline function drm_fb_helper_defio_init()
  drm/i915: Fix an error handling path in igt_write_huge()
  drm/i915/dpt: Use shmem for dpt objects
  drm/msm: Fix hw_fence error path cleanup
  drm/msm: Fix IS_ERR_OR_NULL() vs NULL check in a5xx_submit_in_rb()
  drm/msm/adreno: Fix snapshot BINDLESS_DATA size
  drm/msm/a690: Remove revn and name
  drm/msm/adreno: Fix warn splat for devices without revn
  drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config
  drm/msm/dpu: drop enum dpu_core_perf_data_bus_id
  ...
parents f24767ca 9a767faa

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −3
Original line number Diff line number Diff line
@@ -498,11 +498,11 @@ static int psp_sw_init(void *handle) 
	return 0;



failed2:

	amdgpu_bo_free_kernel(&psp->fw_pri_bo,

			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);

failed1:

	amdgpu_bo_free_kernel(&psp->fence_buf_bo,

			      &psp->fence_buf_mc_addr, &psp->fence_buf);

failed1:

	amdgpu_bo_free_kernel(&psp->fw_pri_bo,

			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);

	return ret;

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+2 −1
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L



#define GOLDEN_GB_ADDR_CONFIG 0x2a114042

#define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301



struct amdgpu_gfx_ras gfx_v9_4_3_ras;
@@ -1736,7 +1737,7 @@ static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 


	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

+1 −4
Original line number Diff line number Diff line
@@ -402,18 +402,15 @@ static void gfxhub_v1_2_xcc_program_invalidation(struct amdgpu_device *adev, 
static int gfxhub_v1_2_xcc_gart_enable(struct amdgpu_device *adev,

				       uint32_t xcc_mask)

{

	uint32_t tmp_mask;

	int i;



	tmp_mask = xcc_mask;

	/*

	 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, because they are

	 * VF copy registers so vbios post doesn't program them, for

	 * SRIOV driver need to program them

	 */

	if (amdgpu_sriov_vf(adev)) {

		for_each_inst(i, tmp_mask) {

			i = ffs(tmp_mask) - 1;

		for_each_inst(i, xcc_mask) {

			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE,

				     adev->gmc.vram_start >> 24);

			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP,

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

+2 −3
Original line number Diff line number Diff line
@@ -302,8 +302,7 @@ static int kfd_dbg_set_queue_workaround(struct queue *q, bool enable) 
	if (!q)

		return 0;



	if (KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) ||

	    KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0))

	if (!kfd_dbg_has_cwsr_workaround(q->device))

		return 0;



	if (enable && q->properties.is_user_cu_masked)
@@ -349,7 +348,7 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd) 
{

	uint32_t spi_dbg_cntl = pdd->spi_dbg_override | pdd->spi_dbg_launch_mode;

	uint32_t flags = pdd->process->dbg_flags;

	bool sq_trap_en = !!spi_dbg_cntl;

	bool sq_trap_en = !!spi_dbg_cntl || !kfd_dbg_has_cwsr_workaround(pdd->dev);



	if (!kfd_dbg_is_per_vmid_supported(pdd->dev))

		return 0;

drivers/gpu/drm/amd/amdkfd/kfd_debug.h

+6 −0
Original line number Diff line number Diff line
@@ -100,6 +100,12 @@ static inline bool kfd_dbg_is_rlc_restore_supported(struct kfd_node *dev) 
		 KFD_GC_VERSION(dev) == IP_VERSION(10, 1, 1));

}



static inline bool kfd_dbg_has_cwsr_workaround(struct kfd_node *dev)

{

	return KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0) &&

	       KFD_GC_VERSION(dev) <= IP_VERSION(11, 0, 3);

}



static inline bool kfd_dbg_has_gws_support(struct kfd_node *dev)

{

	if ((KFD_GC_VERSION(dev) == IP_VERSION(9, 0, 1)