Commit 9a767faa authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2023-07-27' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v6.5-rc4

Display:
+ Fix to correct the UBWC programming for decoder version 4.3 seen
  on SM8550
+ Add the missing flush and fetch bits for DMA4 and DMA5 SSPPs.
+ Fix to drop the unused dpu_core_perf_data_bus_id enum from the code
+ Drop the unused dsi_phy_14nm_17mA_regulators from QCM 2290 DSI cfg.

GPU:
+ Fix warn splat for newer devices without revn
+ Remove name/revn for a690.. we shouldn't be populating these for
  newer devices, for consistency, but it slipped through review
+ Fix a6xx gpu snapshot BINDLESS_DATA size (was listed in bytes
  instead of dwords, causing AHB faults on a6xx gen4/a660-family)
+ Disallow submit with fence id 0

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs9MwCSfiyv8i7yWAsJKYEzCDyzaTx=ujX80Y23rZd9RA@mail.gmail.com
parents 0dd9c514 1b5d0ddc

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit 
			 * since we've already mapped it once in

			 * submit_reloc()

			 */

			if (WARN_ON(!ptr))

			if (WARN_ON(IS_ERR_OR_NULL(ptr)))

				return;



			for (i = 0; i < dwords; i++) {

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+1 −1
Original line number Diff line number Diff line
@@ -206,7 +206,7 @@ static const struct a6xx_shader_block { 
	SHADER(A6XX_SP_LB_3_DATA, 0x800),

	SHADER(A6XX_SP_LB_4_DATA, 0x800),

	SHADER(A6XX_SP_LB_5_DATA, 0x200),

	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),

	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),

	SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),

	SHADER(A6XX_SP_UAV_DATA, 0x80),

	SHADER(A6XX_SP_INST_TAG, 0x80),

drivers/gpu/drm/msm/adreno/adreno_device.c

+0 −2
Original line number Diff line number Diff line
@@ -369,8 +369,6 @@ static const struct adreno_info gpulist[] = { 
		.hwcg = a640_hwcg,

	}, {

		.rev = ADRENO_REV(6, 9, 0, ANY_ID),

		.revn = 690,

		.name = "A690",

		.fw = {

			[ADRENO_FW_SQE] = "a660_sqe.fw",

			[ADRENO_FW_GMU] = "a690_gmu.bin",

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+8 −4
Original line number Diff line number Diff line
@@ -149,7 +149,8 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); 


static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return gpu->revn == revn;

}
@@ -161,14 +162,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) 


static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return (gpu->revn < 300);

}



static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return (gpu->revn < 210);

}
@@ -307,7 +310,8 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu) 


static inline int adreno_is_a690(const struct adreno_gpu *gpu)

{

	return adreno_is_revn(gpu, 690);

	/* The order of args is important here to handle ANY_ID correctly */

	return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);

};



/* check for a615, a616, a618, a619 or any derivatives */

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

+0 −13
Original line number Diff line number Diff line
@@ -14,19 +14,6 @@ 


#define	DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE	412500000



/**

 * enum dpu_core_perf_data_bus_id - data bus identifier

 * @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus

 * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus

 * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus

 */

enum dpu_core_perf_data_bus_id {

	DPU_CORE_PERF_DATA_BUS_ID_MNOC,

	DPU_CORE_PERF_DATA_BUS_ID_LLCC,

	DPU_CORE_PERF_DATA_BUS_ID_EBI,

	DPU_CORE_PERF_DATA_BUS_ID_MAX,

};



/**

 * struct dpu_core_perf_params - definition of performance parameters

 * @max_per_pipe_ib: maximum instantaneous bandwidth request