Commit 17180961 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu',... 

Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi' and 'msm-next-lumag-mdp5' into msm-next-lumag
parents d89e5028 050770cb d8c2f094 bb07af2e 088604d3 16b323dd

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
      - qcom,sc7280-edp

      - qcom,sc8180x-dp

      - qcom,sc8180x-edp

      - qcom,sm8350-dp



  reg:

    items:

Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml

0 → 100644
+219 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DPU dt properties for MSM8998 target



maintainers:

  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>



description: |

  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates

  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree

  bindings of MDSS and DPU are mentioned for MSM8998 target.



properties:

  compatible:

    items:

      - const: qcom,msm8998-mdss



  reg:

    maxItems: 1



  reg-names:

    const: mdss



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: Display AHB clock

      - description: Display AXI clock

      - description: Display core clock



  clock-names:

    items:

      - const: iface

      - const: bus

      - const: core



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#address-cells": true



  "#size-cells": true



  "#interrupt-cells":

    const: 1



  iommus:

    items:

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0



  ranges: true



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    description: Node containing the properties of DPU.



    properties:

      compatible:

        items:

          - const: qcom,msm8998-dpu



      reg:

        items:

          - description: Address offset and size for mdp register set

          - description: Address offset and size for regdma register set

          - description: Address offset and size for vbif register set

          - description: Address offset and size for non-realtime vbif register set



      reg-names:

        items:

          - const: mdp

          - const: regdma

          - const: vbif

          - const: vbif_nrt



      clocks:

        items:

          - description: Display ahb clock

          - description: Display axi clock

          - description: Display mem-noc clock

          - description: Display core clock

          - description: Display vsync clock



      clock-names:

        items:

          - const: iface

          - const: bus

          - const: mnoc

          - const: core

          - const: vsync



      interrupts:

        maxItems: 1



      power-domains:

        maxItems: 1



      operating-points-v2: true

      ports:

        $ref: /schemas/graph.yaml#/properties/ports

        description: |

          Contains the list of output ports from DPU device. These ports

          connect to interfaces that are external to the DPU hardware,

          such as DSI, DP etc. Each output port contains an endpoint that

          describes how it is connected to an external interface.



        properties:

          port@0:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF1 (DSI1)



          port@1:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF2 (DSI2)



        required:

          - port@0

          - port@1



    required:

      - compatible

      - reg

      - reg-names

      - clocks

      - interrupts

      - power-domains

      - operating-points-v2

      - ports



required:

  - compatible

  - reg

  - reg-names

  - power-domains

  - clocks

  - interrupts

  - interrupt-controller

  - iommus

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@c900000 {

        compatible = "qcom,msm8998-mdss";

        reg = <0x0c900000 0x1000>;

        reg-names = "mdss";



        clocks = <&mmcc MDSS_AHB_CLK>,

                 <&mmcc MDSS_AXI_CLK>,

                 <&mmcc MDSS_MDP_CLK>;

        clock-names = "iface", "bus", "core";



        #address-cells = <1>;

        #interrupt-cells = <1>;

        #size-cells = <1>;



        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        iommus = <&mmss_smmu 0>;



        power-domains = <&mmcc MDSS_GDSC>;

        ranges;



        display-controller@c901000 {

            compatible = "qcom,msm8998-dpu";

            reg = <0x0c901000 0x8f000>,

                  <0x0c9a8e00 0xf0>,

                  <0x0c9b0000 0x2008>,

                  <0x0c9b8000 0x1040>;

            reg-names = "mdp", "regdma", "vbif", "vbif_nrt";



            clocks = <&mmcc MDSS_AHB_CLK>,

                     <&mmcc MDSS_AXI_CLK>,

                     <&mmcc MNOC_AHB_CLK>,

                     <&mmcc MDSS_MDP_CLK>,

                     <&mmcc MDSS_VSYNC_CLK>;

            clock-names = "iface", "bus", "mnoc", "core", "vsync";



            interrupt-parent = <&mdss>;

            interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

            operating-points-v2 = <&mdp_opp_table>;

            power-domains = <&rpmpd MSM8998_VDDMX>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    dpu_intf1_out: endpoint {

                        remote-endpoint = <&dsi0_in>;

                    };

                };



                port@1 {

                    reg = <1>;

                    dpu_intf2_out: endpoint {

                        remote-endpoint = <&dsi1_in>;

                    };

                };

            };

        };

    };

...

Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml

+36 −0
Original line number Diff line number Diff line
@@ -35,6 +35,38 @@ properties: 
      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and

      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target



  qcom,phy-rescode-offset-top:

    $ref: /schemas/types.yaml#/definitions/int8-array

    minItems: 5

    maxItems: 5

    description:

      Integer array of offset for pull-up legs rescode for all five lanes.

      To offset the drive strength from the calibrated value in an increasing

      manner, -32 is the weakest and +31 is the strongest.

    items:

      minimum: -32

      maximum: 31



  qcom,phy-rescode-offset-bot:

    $ref: /schemas/types.yaml#/definitions/int8-array

    minItems: 5

    maxItems: 5

    description:

      Integer array of offset for pull-down legs rescode for all five lanes.

      To offset the drive strength from the calibrated value in a decreasing

      manner, -32 is the weakest and +31 is the strongest.

    items:

      minimum: -32

      maximum: 31



  qcom,phy-drive-ldo-level:

    $ref: "/schemas/types.yaml#/definitions/uint32"

    description:

      The PHY LDO has an amplitude tuning feature to adjust the LDO output

      for the HSTX drive. Use supported levels (mV) to offset the drive level

      from the default value.

    enum: [ 375, 400, 425, 450, 475, 500 ]



required:

  - compatible

  - reg
@@ -64,5 +96,9 @@ examples: 
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                  <&rpmhcc RPMH_CXO_CLK>;

         clock-names = "iface", "ref";



         qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;

         qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;

         qcom,phy-drive-ldo-level = <400>;

     };

...

drivers/gpu/drm/msm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,6 @@ msm-y := \ 
	disp/dpu1/dpu_hw_top.o \

	disp/dpu1/dpu_hw_util.o \

	disp/dpu1/dpu_hw_vbif.o \

	disp/dpu1/dpu_io_util.o \

	disp/dpu1/dpu_kms.o \

	disp/dpu1/dpu_mdss.o \

	disp/dpu1/dpu_plane.o \
@@ -103,6 +102,7 @@ msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o 


msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \

	dp/dp_catalog.o \

	dp/dp_clk_util.o \

	dp/dp_ctrl.o \

	dp/dp_display.o \

	dp/dp_drm.o \

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

+6 −17
Original line number Diff line number Diff line
@@ -284,17 +284,6 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) 
	}

}



static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)

{

	struct dss_clk *core_clk = kms->perf.core_clk;



	if (core_clk->max_rate && (rate > core_clk->max_rate))

		rate = core_clk->max_rate;



	core_clk->rate = rate;

	return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);

}



static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)

{

	u64 clk_rate = kms->perf.perf_tune.min_core_clk;
@@ -306,7 +295,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) 
			dpu_cstate = to_dpu_crtc_state(crtc->state);

			clk_rate = max(dpu_cstate->new_perf.core_clk_rate,

							clk_rate);

			clk_rate = clk_round_rate(kms->perf.core_clk->clk,

			clk_rate = clk_round_rate(kms->perf.core_clk,

					clk_rate);

		}

	}
@@ -405,10 +394,10 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 


		trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);



		ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate);

		clk_rate = min(clk_rate, kms->perf.max_core_clk_rate);

		ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate);

		if (ret) {

			DPU_ERROR("failed to set %s clock rate %llu\n",

					kms->perf.core_clk->clk_name, clk_rate);

			DPU_ERROR("failed to set core clock rate %llu\n", clk_rate);

			return ret;

		}
@@ -529,13 +518,13 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) 
int dpu_core_perf_init(struct dpu_core_perf *perf,

		struct drm_device *dev,

		struct dpu_mdss_cfg *catalog,

		struct dss_clk *core_clk)

		struct clk *core_clk)

{

	perf->dev = dev;

	perf->catalog = catalog;

	perf->core_clk = core_clk;



	perf->max_core_clk_rate = core_clk->max_rate;

	perf->max_core_clk_rate = clk_get_rate(core_clk);

	if (!perf->max_core_clk_rate) {

		DPU_DEBUG("optional max core clk rate, use default\n");

		perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;