Commit 165ab7b4 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

Revert "drm/amd/display: Pass the new context into disable OTG WA" 



This reverts commit 8440f575.

Causes a hang when hotplugging DP, shutting down system, or
enabling dual eDP.

Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ae204faa

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -99,13 +99,13 @@ static int dcn31_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -211,11 +211,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn31_disable_otg_wa(clk_mgr_base, context, true);

		dcn31_disable_otg_wa(clk_mgr_base, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn31_disable_otg_wa(clk_mgr_base, context, false);

		dcn31_disable_otg_wa(clk_mgr_base, false);



		update_dispclk = true;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -79,13 +79,13 @@ static int dcn315_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -173,11 +173,11 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn315_disable_otg_wa(clk_mgr_base, context, true);

		dcn315_disable_otg_wa(clk_mgr_base, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn315_disable_otg_wa(clk_mgr_base, context, false);

		dcn315_disable_otg_wa(clk_mgr_base, false);



		update_dispclk = true;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -112,13 +112,13 @@ static int dcn316_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -221,11 +221,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn316_disable_otg_wa(clk_mgr_base, context, true);

		dcn316_disable_otg_wa(clk_mgr_base, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn316_disable_otg_wa(clk_mgr_base, context, false);

		dcn316_disable_otg_wa(clk_mgr_base, false);



		update_dispclk = true;

	}