Unverified Commit 1631ba12 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
Browse files

riscv: Add support for non-coherent devices using zicbom extension 



The Zicbom ISA-extension was ratified in november 2021
and introduces instructions for dcache invalidate, clean
and flush operations.

Implement cache management operations for non-coherent devices
based on them.

Of course not all cores will support this, so implement an
alternative-based mechanism that replaces empty instructions
with ones done around Zicbom instructions.

As discussed in previous versions, assume the platform
being coherent by default so that non-coherent devices need
to get marked accordingly by firmware.

Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent d1afce67

arch/riscv/Kconfig

+31 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ config RISCV 
	select MODULES_USE_ELF_RELA if MODULES

	select MODULE_SECTIONS if MODULES

	select OF

	select OF_DMA_DEFAULT_COHERENT

	select OF_EARLY_FLATTREE

	select OF_IRQ

	select PCI_DOMAINS_GENERIC if PCI
@@ -218,6 +219,14 @@ config PGTABLE_LEVELS 
config LOCKDEP_SUPPORT

	def_bool y



config RISCV_DMA_NONCOHERENT

	bool

	select ARCH_HAS_DMA_PREP_COHERENT

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SETUP_DMA_OPS

	select DMA_DIRECT_REMAP



source "arch/riscv/Kconfig.socs"

source "arch/riscv/Kconfig.erratas"
@@ -376,6 +385,28 @@ config RISCV_ISA_SVPBMT 


	   If you don't know what to do here, say Y.



config CC_HAS_ZICBOM

	bool

	default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom)

	default y if 32BIT && $(cc-option,-mabi=ilp32 -march=rv32ima_zicbom)



config RISCV_ISA_ZICBOM

	bool "Zicbom extension support for non-coherent DMA operation"

	depends on CC_HAS_ZICBOM

	depends on !XIP_KERNEL

	select RISCV_DMA_NONCOHERENT

	select RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZICBOM

	   extension (Cache Block Management Operations) and enable its

	   usage.



	   The Zicbom extension can be used to handle for example

	   non-coherent DMA support on devices that need it.



	   If you don't know what to do here, say Y.



config FPU

	bool "FPU support"

	default y

arch/riscv/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c 
toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)

riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei



# Check if the toolchain supports Zicbom extension

toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom)

riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom



KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))

KBUILD_AFLAGS += -march=$(riscv-march-y)

arch/riscv/include/asm/cache.h

+4 −0
Original line number Diff line number Diff line
@@ -11,6 +11,10 @@ 


#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



#ifdef CONFIG_RISCV_DMA_NONCOHERENT

#define ARCH_DMA_MINALIGN L1_CACHE_BYTES

#endif



/*

 * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that

 * the flat loader aligns it accordingly.

arch/riscv/include/asm/cacheflush.h

+10 −0
Original line number Diff line number Diff line
@@ -42,6 +42,16 @@ void flush_icache_mm(struct mm_struct *mm, bool local); 


#endif /* CONFIG_SMP */



#ifdef CONFIG_RISCV_ISA_ZICBOM

void riscv_init_cbom_blocksize(void);

#else

static inline void riscv_init_cbom_blocksize(void) { }

#endif



#ifdef CONFIG_RISCV_DMA_NONCOHERENT

void riscv_noncoherent_supported(void);

#endif



/*

 * Bits in sys_riscv_flush_icache()'s flags argument.

 */

arch/riscv/include/asm/errata_list.h

+18 −1
Original line number Diff line number Diff line
@@ -20,7 +20,8 @@ 
#endif



#define	CPUFEATURE_SVPBMT 0

#define	CPUFEATURE_NUMBER 1

#define	CPUFEATURE_ZICBOM 1

#define	CPUFEATURE_NUMBER 2



#ifdef __ASSEMBLY__
@@ -93,6 +94,22 @@ asm volatile(ALTERNATIVE( \ 
#define ALT_THEAD_PMA(_val)

#endif



#define ALT_CMO_OP(_op, _start, _size, _cachesize)			\

asm volatile(ALTERNATIVE(						\

	__nops(5),							\

	"mv a0, %1\n\t"							\

	"j 2f\n\t"							\

	"3:\n\t"							\

	"cbo." __stringify(_op) " (a0)\n\t"				\

	"add a0, a0, %0\n\t"						\

	"2:\n\t"							\

	"bltu a0, %2, 3b\n\t", 0,					\

		CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM)		\

	: : "r"(_cachesize),						\

	    "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)),	\

	    "r"((unsigned long)(_start) + (_size))			\

	: "a0")



#endif /* __ASSEMBLY__ */



#endif