Unverified Commit d1afce67 authored Jul 07, 2022 by Heiko Stuebner Committed by Palmer Dabbelt Jul 28, 2022

dt-bindings: riscv: document cbom-block-size



The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.

So add the necessary property for the system to know the core's
block-size.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220706231536.2041855-3-heiko@sntech.de


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent 12b82775

Documentation/devicetree/bindings/riscv/cpus.yaml

+5 −0

Original line number	Diff line number	Diff line
		@@ -63,6 +63,11 @@ properties:
		- riscv,sv48
		- riscv,none

		riscv,cbom-block-size:
		$ref: /schemas/types.yaml#/definitions/uint32
		description:
		The blocksize in bytes for the Zicbom cache operations.

		riscv,isa:
		description:
		Identifies the specific RISC-V instruction set architecture