Commit 148816f9 authored by Wyatt Wood's avatar Wyatt Wood Committed by Alex Deucher
Browse files

drm/amd/display: Initialize dmub_rb_cmd unions to 0 



[Why]
Since dmub_rb_cmds are not initialized to 0,
the header is filled with invalid data.
This is causing issues on the fw side.

[How]
Initialize dmub_rb_cmd unions to 0.

Signed-off-by: default avatarWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: default avatarJosip Pavic <Josip.Pavic@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7a03fdf6

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

+3 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) 
	union dmub_rb_cmd cmd;

	uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;



	memset(&cmd, 0, sizeof(cmd));

	cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;

	cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;

	cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm;
@@ -135,6 +136,7 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level) 
	union dmub_rb_cmd cmd;

	struct dc_context *dc = abm->ctx;



	memset(&cmd, 0, sizeof(cmd));

	cmd.abm_set_level.header.type = DMUB_CMD__ABM;

	cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL;

	cmd.abm_set_level.abm_set_level_data.level = level;
@@ -160,6 +162,7 @@ static bool dmub_abm_init_config(struct abm *abm, 
	// Copy iramtable into cw7

	memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);



	memset(&cmd, 0, sizeof(cmd));

	// Fw will copy from cw7 to fw_state

	cmd.abm_init_config.header.type = DMUB_CMD__ABM;

	cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG;

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

+2 −1
Original line number Diff line number Diff line
@@ -33,8 +33,9 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, 
				union dmub_hw_lock_flags *hw_locks,

				struct dmub_hw_lock_inst_flags *inst_flags)

{

	union dmub_rb_cmd cmd = { 0 };

	union dmub_rb_cmd cmd;



	memset(&cmd, 0, sizeof(cmd));

	cmd.lock_hw.header.type = DMUB_CMD__HW_LOCK;

	cmd.lock_hw.header.sub_type = 0;

	cmd.lock_hw.header.payload_bytes = sizeof(struct dmub_cmd_lock_hw_data);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

+5 −1
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state * 
	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)

		return false;



	memset(&cmd, 0, sizeof(cmd));

	cmd.psr_set_version.header.type = DMUB_CMD__PSR;

	cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;

	switch (stream->link->psr_settings.psr_version) {
@@ -131,7 +132,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) 
	uint32_t retry_count;

	enum dc_psr_state state = PSR_STATE0;





	memset(&cmd, 0, sizeof(cmd));

	cmd.psr_enable.header.type = DMUB_CMD__PSR;



	if (enable)
@@ -184,6 +185,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) 
	if (state == PSR_STATE0)

		return;



	memset(&cmd, 0, sizeof(cmd));

	cmd.psr_set_level.header.type = DMUB_CMD__PSR;

	cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;

	cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
@@ -233,6 +235,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 
	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

			psr_context->sdpTransmitLineNumDeadline);



	memset(&cmd, 0, sizeof(cmd));

	cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;

	cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;

	cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
@@ -285,6 +288,7 @@ static void dmub_psr_force_static(struct dmub_psr *dmub) 
	union dmub_rb_cmd cmd;

	struct dc_context *dc = dmub->ctx;



	memset(&cmd, 0, sizeof(cmd));

	cmd.psr_force_static.header.type = DMUB_CMD__PSR;

	cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;

	cmd.psr_enable.header.payload_bytes = 0;

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c

+3 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ void dcn21_optimize_pwr_state( 
 * PHY will hang on the next mode set attempt.

 * if enable PLL follow by disable PLL (without executing lane enable/disable),

 * RDPCS_PHY_DP_MPLLB_STATE remains 1,

 * which indicate that PLL disable attempt actually didnt go through.

 * which indicate that PLL disable attempt actually didn't go through.

 * As a workaround, insert PHY lane enable/disable before PLL disable.

 */

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)
@@ -143,6 +143,7 @@ static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t optio 
	struct dc_context *dc = abm->ctx;

	uint32_t ramping_boundary = 0xFFFF;



	memset(&cmd, 0, sizeof(cmd));

	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;

	cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;

	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
@@ -212,6 +213,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, 
	if (abm && panel_cntl)

		dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst);



	memset(&cmd, 0, sizeof(cmd));

	cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;

	cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;

	cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;