Commit 7a03fdf6 authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher
Browse files

drm/amd/display: fix 64bit division issue on 32bit OS 



Replace "/" with div_u64 for 64bit division on 32bit OS.

Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6fce5bce

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+2 −2
Original line number Diff line number Diff line
@@ -3688,8 +3688,8 @@ uint32_t dc_link_bandwidth_kbps( 
		 * but the difference is minimal and is in a safe direction,

		 * which all works well around potential ambiguity of DP 1.4a spec.

		 */

		link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,

					       link_bw_kbps, 32);

		long long fec_link_bw_kbps = link_bw_kbps * 970LL;

		link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));

	}



	return link_bw_kbps;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+1 −1
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static bool calc_fb_divider_checking_tolerance( 
		pll_settings->calculated_pix_clk_100hz =

			actual_calculated_clock_100hz;

		pll_settings->vco_freq =

			actual_calculated_clock_100hz * post_divider / 10;

			div_u64(actual_calculated_clock_100hz * post_divider, 10);

		return true;

	}

	return false;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -3506,7 +3506,8 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s 
		calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;



		// FCLK:UCLK ratio is 1.08

		min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);

		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,

			1000000);



		calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?

				min_dcfclk : min_fclk_required_by_uclk;