Commit 1436de0b authored by Eran Ben Elisha's avatar Eran Ben Elisha Committed by Saeed Mahameed
Browse files

net/mlx5: Refactor init clock function 



Function mlx5_init_clock() is responsible for internal PTP related metadata
initializations. Break mlx5_init_clock() to sub functions, each takes care
of its own logic.

Signed-off-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarAya Levin <ayal@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent ae02d415

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

+53 −23
Original line number Diff line number Diff line
@@ -591,20 +591,12 @@ static int mlx5_pps_event(struct notifier_block *nb, 
	return NOTIFY_OK;

}



void mlx5_init_clock(struct mlx5_core_dev *mdev)

static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)

{

	struct mlx5_clock *clock = &mdev->clock;

	u64 overflow_cycles;

	u64 ns;

	u64 frac = 0;

	u32 dev_freq;



	dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);

	if (!dev_freq) {

		mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");

		return;

	}

	seqlock_init(&clock->lock);

	clock->cycles.read = read_internal_timer;

	clock->cycles.shift = MLX5_CYCLES_SHIFT;

	clock->cycles.mult = clocksource_khz2mult(dev_freq,
@@ -614,6 +606,15 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev) 


	timecounter_init(&clock->tc, &clock->cycles,

			 ktime_to_ns(ktime_get_real()));

}



static void mlx5_init_overflow_period(struct mlx5_clock *clock)

{

	struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);

	struct mlx5_ib_clock_info *clock_info = mdev->clock_info;

	u64 overflow_cycles;

	u64 frac = 0;

	u64 ns;



	/* Calculate period in seconds to call the overflow watchdog - to make

	 * sure counter is checked at least twice every wrap around.
@@ -630,24 +631,53 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev) 
	do_div(ns, NSEC_PER_SEC / HZ);

	clock->overflow_period = ns;



	mdev->clock_info =

		(struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);

	if (mdev->clock_info) {

		mdev->clock_info->nsec = clock->tc.nsec;

		mdev->clock_info->cycles = clock->tc.cycle_last;

		mdev->clock_info->mask = clock->cycles.mask;

		mdev->clock_info->mult = clock->nominal_c_mult;

		mdev->clock_info->shift = clock->cycles.shift;

		mdev->clock_info->frac = clock->tc.frac;

		mdev->clock_info->overflow_period = clock->overflow_period;

	}



	INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);

	INIT_DELAYED_WORK(&clock->overflow_work, mlx5_timestamp_overflow);

	if (clock->overflow_period)

		schedule_delayed_work(&clock->overflow_work, 0);

	else

		mlx5_core_warn(mdev, "invalid overflow period, overflow_work is not scheduled\n");

		mlx5_core_warn(mdev,

			       "invalid overflow period, overflow_work is not scheduled\n");



	if (clock_info)

		clock_info->overflow_period = clock->overflow_period;

}



static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)

{

	struct mlx5_clock *clock = &mdev->clock;

	struct mlx5_ib_clock_info *info;



	mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);

	if (!mdev->clock_info) {

		mlx5_core_warn(mdev, "Failed to allocate IB clock info page\n");

		return;

	}



	info = mdev->clock_info;



	info->nsec = clock->tc.nsec;

	info->cycles = clock->tc.cycle_last;

	info->mask = clock->cycles.mask;

	info->mult = clock->nominal_c_mult;

	info->shift = clock->cycles.shift;

	info->frac = clock->tc.frac;

}



void mlx5_init_clock(struct mlx5_core_dev *mdev)

{

	struct mlx5_clock *clock = &mdev->clock;



	if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) {

		mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");

		return;

	}



	seqlock_init(&clock->lock);



	mlx5_timecounter_init(mdev);

	mlx5_init_clock_info(mdev);

	mlx5_init_overflow_period(clock);

	INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);



	/* Configure the PHC */

	clock->ptp_info = mlx5_ptp_clock_info;