Commit 13e248aa authored by Will Deacon's avatar Will Deacon Committed by Marc Zyngier
Browse files

KVM: arm64: Provide I-cache invalidation by virtual address at EL2 



In preparation for handling cache maintenance of guest pages from within
the pKVM hypervisor at EL2, introduce an EL2 copy of icache_inval_pou()
which will later be plumbed into the stage-2 page-table cache
maintenance callbacks, ensuring that the initial contents of pages
mapped as executable into the guest stage-2 page-table is visible to the
instruction fetcher.

Tested-by: default avatarVincent Donnefort <vdonnefort@google.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221110190259.26861-17-will@kernel.org
parent 6c165223

arch/arm64/include/asm/kvm_hyp.h

+1 −0
Original line number Diff line number Diff line
@@ -123,4 +123,5 @@ extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val); 
extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val);



extern unsigned long kvm_nvhe_sym(__icache_flags);

#endif /* __ARM64_KVM_HYP_H__ */

arch/arm64/kernel/image-vars.h

+0 −3
Original line number Diff line number Diff line
@@ -71,9 +71,6 @@ KVM_NVHE_ALIAS(nvhe_hyp_panic_handler); 
/* Vectors installed by hyp-init on reset HVC. */

KVM_NVHE_ALIAS(__hyp_stub_vectors);



/* Kernel symbol used by icache_is_vpipt(). */

KVM_NVHE_ALIAS(__icache_flags);



/* VMID bits set by the KVM VMID allocator */

KVM_NVHE_ALIAS(kvm_arm_vmid_bits);

arch/arm64/kvm/arm.c

+1 −0
Original line number Diff line number Diff line
@@ -1894,6 +1894,7 @@ static void kvm_hyp_init_symbols(void) 
	kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);

	kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);

	kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);

	kvm_nvhe_sym(__icache_flags) = __icache_flags;

}



static int kvm_hyp_init_protection(u32 hyp_va_bits)

arch/arm64/kvm/hyp/nvhe/cache.S

+11 −0
Original line number Diff line number Diff line
@@ -12,3 +12,14 @@ SYM_FUNC_START(__pi_dcache_clean_inval_poc) 
	ret

SYM_FUNC_END(__pi_dcache_clean_inval_poc)

SYM_FUNC_ALIAS(dcache_clean_inval_poc, __pi_dcache_clean_inval_poc)



SYM_FUNC_START(__pi_icache_inval_pou)

alternative_if ARM64_HAS_CACHE_DIC

	isb

	ret

alternative_else_nop_endif



	invalidate_icache_by_line x0, x1, x2, x3

	ret

SYM_FUNC_END(__pi_icache_inval_pou)

SYM_FUNC_ALIAS(icache_inval_pou, __pi_icache_inval_pou)

arch/arm64/kvm/hyp/nvhe/pkvm.c

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ 
#include <nvhe/pkvm.h>

#include <nvhe/trap_handler.h>



/* Used by icache_is_vpipt(). */

unsigned long __icache_flags;



/*

 * Set trap register values based on features in ID_AA64PFR0.

 */