Commit 12564485 authored by Shawn Anastasio's avatar Shawn Anastasio Committed by Michael Ellerman
Browse files

Revert "powerpc/64s: Remove PROT_SAO support" 



This reverts commit 5c9fa16e.

Since PROT_SAO can still be useful for certain classes of software,
reintroduce it. Concerns about guest migration for LPARs using SAO
will be addressed next.

Signed-off-by: default avatarShawn Anastasio <shawn@anastas.io>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200821185558.35561-2-shawn@anastas.io
parent 64ef8f2c

arch/powerpc/include/asm/book3s/64/pgtable.h

+3 −5
Original line number Diff line number Diff line
@@ -20,13 +20,9 @@ 
#define _PAGE_RW		(_PAGE_READ | _PAGE_WRITE)

#define _PAGE_RWX		(_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)

#define _PAGE_PRIVILEGED	0x00008 /* kernel access only */



#define _PAGE_CACHE_CTL		0x00030 /* Bits for the folowing cache modes */

			/*	No bits set is normal cacheable memory */

			/*	0x00010 unused, is SAO bit on radix POWER9 */

#define _PAGE_SAO		0x00010 /* Strong access order */

#define _PAGE_NON_IDEMPOTENT	0x00020 /* non idempotent memory */

#define _PAGE_TOLERANT		0x00030 /* tolerant memory, cache inhibited */



#define _PAGE_DIRTY		0x00080 /* C: page changed */

#define _PAGE_ACCESSED		0x00100 /* R: page referenced */

/*
@@ -828,6 +824,8 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 
	return hash__set_pte_at(mm, addr, ptep, pte, percpu);

}



#define _PAGE_CACHE_CTL	(_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)



#define pgprot_noncached pgprot_noncached

static inline pgprot_t pgprot_noncached(pgprot_t prot)

{

arch/powerpc/include/asm/cputable.h

+5 −5
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0000000001000000)

#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0000000002000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0000000004000000)

// Free					LONG_ASM_CONST(0x0000000008000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0000000008000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0000000010000000)

#define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0000000020000000)

#define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0000000040000000)
@@ -441,7 +441,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | \

	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
@@ -450,7 +450,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \

	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
@@ -461,7 +461,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \

	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
@@ -479,7 +479,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \

	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \

arch/powerpc/include/asm/mman.h

+22 −4
Original line number Diff line number Diff line
@@ -13,20 +13,38 @@ 
#include <linux/pkeys.h>

#include <asm/cpu_has_feature.h>



#ifdef CONFIG_PPC_MEM_KEYS

static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot,

		unsigned long pkey)

{

	return pkey_to_vmflag_bits(pkey);

#ifdef CONFIG_PPC_MEM_KEYS

	return (((prot & PROT_SAO) ? VM_SAO : 0) | pkey_to_vmflag_bits(pkey));

#else

	return ((prot & PROT_SAO) ? VM_SAO : 0);

#endif

}

#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey)



static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)

{

	return __pgprot(vmflag_to_pte_pkey_bits(vm_flags));

#ifdef CONFIG_PPC_MEM_KEYS

	return (vm_flags & VM_SAO) ?

		__pgprot(_PAGE_SAO | vmflag_to_pte_pkey_bits(vm_flags)) :

		__pgprot(0 | vmflag_to_pte_pkey_bits(vm_flags));

#else

	return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : __pgprot(0);

#endif

}

#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)

#endif



static inline bool arch_validate_prot(unsigned long prot, unsigned long addr)

{

	if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))

		return false;

	if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))

		return false;

	return true;

}

#define arch_validate_prot arch_validate_prot



#endif /* CONFIG_PPC64 */

#endif	/* _ASM_POWERPC_MMAN_H */

arch/powerpc/include/asm/nohash/64/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -82,6 +82,8 @@ 
 */

#include <asm/nohash/pte-book3e.h>



#define _PAGE_SAO	0



#define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))



/*

arch/powerpc/include/uapi/asm/mman.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#include <asm-generic/mman-common.h>





#define PROT_SAO	0x10		/* Unsupported since v5.9 */

#define PROT_SAO	0x10		/* Strong Access Ordering */



#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */

#define MAP_NORESERVE   0x40            /* don't reserve swap pages */