Commit 12458e35 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2021-02-07' of https://gitlab.freedesktop.org/drm/msm into drm-next 



* a6xx speedbin support
* a508, a509, a512 support
* various a5xx fixes
* various dpu fixes
* qseed3lite support for sm8250
* dsi fix for msm8994
* mdp5 fix for framerate bug with cmd mode panels
* a6xx GMU OOB race fixes that were showing up in CI
* various addition and removal of semicolons
* gem submit fix for legacy userspace relocs path

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvh3tvLz_xtk=4x9xUfo2h2s4xkniOvC7HyLO2jrXnXkw@mail.gmail.com
parents f730f39e 182b4a2d

drivers/gpu/drm/msm/adreno/a5xx.xml.h

+2 −0
Original line number Diff line number Diff line
@@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 


#define REG_A5XX_UCHE_ADDR_MODE_CNTL				0x00000e80



#define REG_A5XX_UCHE_MODE_CNTL					0x00000e81



#define REG_A5XX_UCHE_SVM_CNTL					0x00000e82



#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO			0x00000e87

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+170 −25
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
	a5xx_preempt_trigger(gpu);

}



static const struct {

static const struct adreno_five_hwcg_regs {

	u32 offset;

	u32 value;

} a5xx_hwcg[] = {
@@ -318,16 +318,124 @@ static const struct { 
	{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

}, a50x_hwcg[] = {

	{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},

	{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

}, a512_hwcg[] = {

	{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

};



void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	unsigned int i;

	const struct adreno_five_hwcg_regs *regs;

	unsigned int i, sz;



	if (adreno_is_a508(adreno_gpu)) {

		regs = a50x_hwcg;

		sz = ARRAY_SIZE(a50x_hwcg);

	} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {

		regs = a512_hwcg;

		sz = ARRAY_SIZE(a512_hwcg);

	} else {

		regs = a5xx_hwcg;

		sz = ARRAY_SIZE(a5xx_hwcg);

	}



	for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)

		gpu_write(gpu, a5xx_hwcg[i].offset,

			state ? a5xx_hwcg[i].value : 0);

	for (i = 0; i < sz; i++)

		gpu_write(gpu, regs[i].offset,

			  state ? regs[i].value : 0);



	if (adreno_is_a540(adreno_gpu)) {

		gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0);
@@ -538,11 +646,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

	u32 regbit;

	int ret;



	gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);



	if (adreno_is_a540(adreno_gpu))

	if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||

	    adreno_is_a540(adreno_gpu))

		gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);



	/* Make all blocks contribute to the GPU BUSY perf counter */
@@ -604,29 +714,48 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
		0x00100000 + adreno_gpu->gmem - 1);

	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);



	if (adreno_is_a510(adreno_gpu)) {

	if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {

		gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);

		if (adreno_is_a508(adreno_gpu))

			gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);

		else

			gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);

		gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);

		gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);

		gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,

			  (0x200 << 11 | 0x200 << 22));

	} else {

		gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);

		if (adreno_is_a530(adreno_gpu))

			gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);

		if (adreno_is_a540(adreno_gpu))

		else

			gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);

		gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);

		gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);

	}



	if (adreno_is_a508(adreno_gpu))

		gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,

			  (0x100 << 11 | 0x100 << 22));

	else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||

		 adreno_is_a512(adreno_gpu))

		gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,

			  (0x200 << 11 | 0x200 << 22));

	else

		gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,

			  (0x400 << 11 | 0x300 << 22));

	}



	if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)

		gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));



	gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);

	/*

	 * Disable the RB sampler datapath DP2 clock gating optimization

	 * for 1-SP GPUs, as it is enabled by default.

	 */

	if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||

	    adreno_is_a512(adreno_gpu))

		gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));



	/* Disable UCHE global filter as SP can invalidate/flush independently */

	gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29));



	/* Enable USE_RETENTION_FLOPS */

	gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
@@ -653,10 +782,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);



	/* Set the highest bank bit */

	gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7);

	gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1);

	if (adreno_is_a540(adreno_gpu))

		gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2);

		regbit = 2;

	else

		regbit = 1;



	gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7);

	gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1);



	if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||

	    adreno_is_a540(adreno_gpu))

		gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit);



	/* Disable All flat shading optimization (ALLFLATOPTDIS) */

	gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10));



	/* Protect registers from the CP */

	gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
@@ -688,12 +827,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 


	/* VPC */

	gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8));

	gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4));

	gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16));



	/* UCHE */

	gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));



	if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu))

	if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||

	    adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) ||

	    adreno_is_a530(adreno_gpu))

		gpu_write(gpu, REG_A5XX_CP_PROTECT(17),

			ADRENO_PROTECT_RW(0x10000, 0x8000));
@@ -735,7 +876,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	if (!adreno_is_a510(adreno_gpu))

	if (!(adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||

	      adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu)))

		a5xx_gpmu_ucode_init(gpu);



	ret = a5xx_ucode_init(gpu);
@@ -1168,7 +1310,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	if (adreno_is_a510(adreno_gpu)) {

	/* Adreno 508, 509, 510, 512 needs manual RBBM sus/res control */

	if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {

		/* Halt the sp_input_clk at HM level */

		gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055);

		a5xx_set_hwcg(gpu, true);
@@ -1210,8 +1353,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) 
	u32 mask = 0xf;

	int i, ret;



	/* A510 has 3 XIN ports in VBIF */

	if (adreno_is_a510(adreno_gpu))

	/* A508, A510 have 3 XIN ports in VBIF */

	if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))

		mask = 0x7;



	/* Clear the VBIF pipe before shutting down */
@@ -1223,10 +1366,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) 


	/*

	 * Reset the VBIF before power collapse to avoid issue with FIFO

	 * entries

	 * entries on Adreno A510 and A530 (the others will tend to lock up)

	 */

	if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) {

		gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);

		gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);

	}



	ret = msm_gpu_pm_suspend(gpu);

	if (ret)

drivers/gpu/drm/msm/adreno/a5xx_power.c

+2 −2
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ int a5xx_power_init(struct msm_gpu *gpu) 
	int ret;



	/* Not all A5xx chips have a GPMU */

	if (adreno_is_a510(adreno_gpu))

	if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))

		return 0;



	/* Set up the limits management */
@@ -330,7 +330,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) 
	unsigned int *data, *ptr, *cmds;

	unsigned int cmds_size;



	if (adreno_is_a510(adreno_gpu))

	if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))

		return;



	if (a5xx_gpu->gpmu_bo)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+62 −43
Original line number Diff line number Diff line
@@ -245,38 +245,67 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 
	return ret;

}



struct a6xx_gmu_oob_bits {

	int set, ack, set_new, ack_new;

	const char *name;

};



/* These are the interrupt / ack bits for each OOB request that are set

 * in a6xx_gmu_set_oob and a6xx_clear_oob

 */

static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {

	[GMU_OOB_GPU_SET] = {

		.name = "GPU_SET",

		.set = 16,

		.ack = 24,

		.set_new = 30,

		.ack_new = 31,

	},



	[GMU_OOB_PERFCOUNTER_SET] = {

		.name = "PERFCOUNTER",

		.set = 17,

		.ack = 25,

		.set_new = 28,

		.ack_new = 30,

	},



	[GMU_OOB_BOOT_SLUMBER] = {

		.name = "BOOT_SLUMBER",

		.set = 22,

		.ack = 30,

	},



	[GMU_OOB_DCVS_SET] = {

		.name = "GPU_DCVS",

		.set = 23,

		.ack = 31,

	},

};



/* Trigger a OOB (out of band) request to the GMU */

int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)

{

	int ret;

	u32 val;

	int request, ack;

	const char *name;



	switch (state) {

	case GMU_OOB_GPU_SET:

	if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))

		return -EINVAL;



	if (gmu->legacy) {

			request = GMU_OOB_GPU_SET_REQUEST;

			ack = GMU_OOB_GPU_SET_ACK;

		request = a6xx_gmu_oob_bits[state].set;

		ack = a6xx_gmu_oob_bits[state].ack;

	} else {

			request = GMU_OOB_GPU_SET_REQUEST_NEW;

			ack = GMU_OOB_GPU_SET_ACK_NEW;

		}

		name = "GPU_SET";

		break;

	case GMU_OOB_BOOT_SLUMBER:

		request = GMU_OOB_BOOT_SLUMBER_REQUEST;

		ack = GMU_OOB_BOOT_SLUMBER_ACK;

		name = "BOOT_SLUMBER";

		break;

	case GMU_OOB_DCVS_SET:

		request = GMU_OOB_DCVS_REQUEST;

		ack = GMU_OOB_DCVS_ACK;

		name = "GPU_DCVS";

		break;

	default:

		request = a6xx_gmu_oob_bits[state].set_new;

		ack = a6xx_gmu_oob_bits[state].ack_new;

		if (!request || !ack) {

			DRM_DEV_ERROR(gmu->dev,

				      "Invalid non-legacy GMU request %s\n",

				      a6xx_gmu_oob_bits[state].name);

			return -EINVAL;

		}

	}



	/* Trigger the equested OOB operation */

	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
@@ -288,7 +317,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 
	if (ret)

		DRM_DEV_ERROR(gmu->dev,

			"Timeout waiting for GMU OOB set %s: 0x%x\n",

				name,

				a6xx_gmu_oob_bits[state].name,

				gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));



	/* Clear the acknowledge interrupt */
@@ -300,27 +329,17 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 
/* Clear a pending OOB state in the GMU */

void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)

{

	if (!gmu->legacy) {

		WARN_ON(state != GMU_OOB_GPU_SET);

		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,

			1 << GMU_OOB_GPU_SET_CLEAR_NEW);

	int bit;



	if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))

		return;

	}



	switch (state) {

	case GMU_OOB_GPU_SET:

		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,

			1 << GMU_OOB_GPU_SET_CLEAR);

		break;

	case GMU_OOB_BOOT_SLUMBER:

		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,

			1 << GMU_OOB_BOOT_SLUMBER_CLEAR);

		break;

	case GMU_OOB_DCVS_SET:

		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,

			1 << GMU_OOB_DCVS_CLEAR);

		break;

	}

	if (gmu->legacy)

		bit = a6xx_gmu_oob_bits[state].ack;

	else

		bit = a6xx_gmu_oob_bits[state].ack_new;



	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit);

}



/* Enable CPU control of SPTP power power collapse */

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

+16 −33
Original line number Diff line number Diff line
@@ -153,43 +153,26 @@ static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) 
 */



enum a6xx_gmu_oob_state {

	GMU_OOB_BOOT_SLUMBER = 0,

	GMU_OOB_GPU_SET,

	GMU_OOB_DCVS_SET,

};



/* These are the interrupt / ack bits for each OOB request that are set

 * in a6xx_gmu_set_oob and a6xx_clear_oob

 */



	/*

	 * Let the GMU know that a boot or slumber operation has started. The value in

	 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are

	 * doing

	 */

#define GMU_OOB_BOOT_SLUMBER_REQUEST	22

#define GMU_OOB_BOOT_SLUMBER_ACK	30

#define GMU_OOB_BOOT_SLUMBER_CLEAR	30



	GMU_OOB_BOOT_SLUMBER = 0,

	/*

	 * Let the GMU know to not turn off any GPU registers while the CPU is in a

	 * critical section

	 */

	GMU_OOB_GPU_SET,

	/*

	 * Set a new power level for the GPU when the CPU is doing frequency scaling

	 */

#define GMU_OOB_DCVS_REQUEST	23

#define GMU_OOB_DCVS_ACK	31

#define GMU_OOB_DCVS_CLEAR	31



	GMU_OOB_DCVS_SET,

	/*

 * Let the GMU know to not turn off any GPU registers while the CPU is in a

 * critical section

	 * Used to keep the GPU on for CPU-side reads of performance counters.

	 */

#define GMU_OOB_GPU_SET_REQUEST	16

#define GMU_OOB_GPU_SET_ACK	24

#define GMU_OOB_GPU_SET_CLEAR	24



#define GMU_OOB_GPU_SET_REQUEST_NEW	30

#define GMU_OOB_GPU_SET_ACK_NEW		31

#define GMU_OOB_GPU_SET_CLEAR_NEW	31



	GMU_OOB_PERFCOUNTER_SET,

};



void a6xx_hfi_init(struct a6xx_gmu *gmu);

int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);