Commit 1121f6b0 authored by Sunil Kumar Kori's avatar Sunil Kumar Kori Committed by David S. Miller
Browse files

octeontx2-af: Priority flow control configuration support 



Prirority based flow control (802.1Qbb)  mechanism is similar to
ethernet pause frames (802.3x) instead pausing all traffic on a link,
PFC allows user to selectively pause traffic according to its class.

Oceteontx2 MAC block (CGX) and CN10K Mac block (RPM) both supports
PFC. As upper layer mbox handler is same for both the MACs, this
patch configures PFC by calling apporopritate callbacks.

Signed-off-by: default avatarSunil Kumar Kori <skori@marvell.com>
Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d957b51f

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+42 −0
Original line number Diff line number Diff line
@@ -817,6 +817,47 @@ static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 
	cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);

}



int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,

			u8 rx_pause, u16 pfc_en)

{

	struct cgx *cgx = cgxd;

	u64 cfg;



	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	/* Return as no traffic classes are requested */

	if (tx_pause && !pfc_en)

		return 0;



	cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);



	if (rx_pause) {

		cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |

			CGXX_SMUX_CBFC_CTL_BCK_EN |

			CGXX_SMUX_CBFC_CTL_DRP_EN);

	} else {

		cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |

			CGXX_SMUX_CBFC_CTL_BCK_EN |

			CGXX_SMUX_CBFC_CTL_DRP_EN);

	}



	if (tx_pause)

		cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;

	else

		cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;



	cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);



	cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);



	/* Write source MAC address which will be filled into PFC packet */

	cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);

	cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);



	return 0;

}



void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)

{

	struct cgx *cgx = cgxd;
@@ -1559,6 +1600,7 @@ static struct mac_ops cgx_mac_ops = { 
	.mac_enadis_ptp_config =	cgx_lmac_ptp_config,

	.mac_rx_tx_enable =		cgx_lmac_rx_tx_enable,

	.mac_tx_enable =		cgx_lmac_tx_enable,

	.pfc_config =                   cgx_lmac_pfc_config,

};



static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+9 −0
Original line number Diff line number Diff line
@@ -76,6 +76,13 @@ 
#define CGXX_SMUX_TX_CTL		0x20178

#define CGXX_SMUX_TX_PAUSE_PKT_TIME	0x20110

#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL	0x20120

#define CGXX_SMUX_SMAC                        0x20108

#define CGXX_SMUX_CBFC_CTL                    0x20218

#define CGXX_SMUX_CBFC_CTL_RX_EN             BIT_ULL(0)

#define CGXX_SMUX_CBFC_CTL_TX_EN             BIT_ULL(1)

#define CGXX_SMUX_CBFC_CTL_DRP_EN            BIT_ULL(2)

#define CGXX_SMUX_CBFC_CTL_BCK_EN            BIT_ULL(3)

#define CGX_PFC_CLASS_MASK		     GENMASK_ULL(47, 32)

#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME	0x38230

#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL	0x38248

#define CGX_SMUX_TX_CTL_L2P_BP_CONV	BIT_ULL(7)
@@ -172,4 +179,6 @@ u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset); 
int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);

u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);

u64 cgx_read_dmac_entry(void *cgxd, int index);

int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,

			u16 pfc_en);

#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h

+3 −0
Original line number Diff line number Diff line
@@ -110,6 +110,9 @@ struct mac_ops { 


	int			(*mac_rx_tx_enable)(void *cgxd, int lmac_id, bool enable);

	int			(*mac_tx_enable)(void *cgxd, int lmac_id, bool enable);

	int                     (*pfc_config)(void *cgxd, int lmac_id,

					      u8 tx_pause, u8 rx_pause, u16 pfc_en);



};



struct cgx {

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+17 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 
M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \

			       msg_rsp)					\

M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \

				 cgx_pfc_rsp)                               \

/* NPA mbox IDs (range 0x400 - 0x5FF) */				\

M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\

				npa_lf_alloc_req, npa_lf_alloc_rsp)	\
@@ -609,6 +611,21 @@ struct rpm_stats_rsp { 
	u64 tx_stats[RPM_TX_STATS_COUNT];

};



struct cgx_pfc_cfg {

	struct mbox_msghdr hdr;

	u8 rx_pause;

	u8 tx_pause;

	u16 pfc_en; /*  bitmap indicating pfc enabled traffic classes */

};



struct cgx_pfc_rsp {

	struct mbox_msghdr hdr;

	u8 rx_pause;

	u8 tx_pause;

};



 /* NPA mbox message formats */



struct npc_set_pkind {

	struct mbox_msghdr hdr;

#define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

+129 −15
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ static struct mac_ops rpm_mac_ops = { 
	.mac_enadis_ptp_config =	rpm_lmac_ptp_config,

	.mac_rx_tx_enable =		rpm_lmac_rx_tx_enable,

	.mac_tx_enable =		rpm_lmac_tx_enable,

	.pfc_config =                   rpm_lmac_pfc_config,

};



struct mac_ops *rpm_get_mac_ops(void)
@@ -129,6 +130,85 @@ int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id, 
	return 0;

}



static void rpm_cfg_pfc_quanta_thresh(rpm_t *rpm, int lmac_id, u16 pfc_en,

				      bool enable)

{

	u64 quanta_offset = 0, quanta_thresh = 0, cfg;

	int i, shift;



	/* Set pause time and interval */

	for_each_set_bit(i, (unsigned long *)&pfc_en, 16) {

		switch (i) {

		case 0:

		case 1:

			quanta_offset = RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL01_QUANTA_THRESH;

			break;

		case 2:

		case 3:

			quanta_offset = RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL23_QUANTA_THRESH;

			break;

		case 4:

		case 5:

			quanta_offset = RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL45_QUANTA_THRESH;

			break;

		case 6:

		case 7:

			quanta_offset = RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL67_QUANTA_THRESH;

			break;

		case 8:

		case 9:

			quanta_offset = RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL89_QUANTA_THRESH;

			break;

		case 10:

		case 11:

			quanta_offset = RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH;

			break;

		case 12:

		case 13:

			quanta_offset = RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH;

			break;

		case 14:

		case 15:

			quanta_offset = RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA;

			quanta_thresh = RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH;

			break;

		}



		if (!quanta_offset || !quanta_thresh)

			continue;



		shift = (i % 2) ? 1 : 0;

		cfg = rpm_read(rpm, lmac_id, quanta_offset);

		if (enable) {

			cfg |= ((u64)RPM_DEFAULT_PAUSE_TIME <<  shift * 16);

		} else {

			if (!shift)

				cfg &= ~GENMASK_ULL(15, 0);

			else

				cfg &= ~GENMASK_ULL(31, 16);

		}

		rpm_write(rpm, lmac_id, quanta_offset, cfg);



		cfg = rpm_read(rpm, lmac_id, quanta_thresh);

		if (enable) {

			cfg |= ((u64)(RPM_DEFAULT_PAUSE_TIME / 2) <<  shift * 16);

		} else {

			if (!shift)

				cfg &= ~GENMASK_ULL(15, 0);

			else

				cfg &= ~GENMASK_ULL(31, 16);

		}

		rpm_write(rpm, lmac_id, quanta_thresh, cfg);

	}

}



int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,

			      u8 rx_pause)

{
@@ -152,8 +232,12 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 


	cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP);

	if (tx_pause) {

		/* Configure CL0 Pause Quanta & threshold for 802.3X frames */

		rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true);

		cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id);

	} else {

		/* Disable all Pause Quanta & threshold values */

		rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);

		cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id);

		cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id);

	}
@@ -166,21 +250,6 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) 
	rpm_t *rpm = rpmd;

	u64 cfg;



	if (enable) {

		/* Set pause time and interval */

		cfg = rpm_read(rpm, lmac_id,

			       RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA);

		cfg &= ~0xFFFFULL;

		rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA,

			  cfg | RPM_DEFAULT_PAUSE_TIME);

		/* Set pause interval as the hardware default is too short */

		cfg = rpm_read(rpm, lmac_id,

			       RPMX_MTI_MAC100X_CL01_QUANTA_THRESH);

		cfg &= ~0xFFFFULL;

		rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_CL01_QUANTA_THRESH,

			  cfg | (RPM_DEFAULT_PAUSE_TIME / 2));

	}



	/* ALL pause frames received are completely ignored */

	cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);

	cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
@@ -302,3 +371,48 @@ void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable) 
		cfg &= ~RPMX_RX_TS_PREPEND;

	rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg);

}



int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en)

{

	rpm_t *rpm = rpmd;

	u64 cfg;



	if (!is_lmac_valid(rpm, lmac_id))

		return -ENODEV;



	/* reset PFC class quanta and threshold */

	rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false);



	cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);



	if (rx_pause) {

		cfg &= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |

				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |

				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);

	} else {

		cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |

				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |

				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);

	}



	if (tx_pause) {

		rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true);

		cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;

	} else {

		rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xfff, false);

		cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;

	}



	if (!rx_pause && !tx_pause)

		cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;

	else

		cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;



	rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);



	cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL);

	cfg = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, cfg);

	rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg);



	return 0;

}