Commit 0fa9349d authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by John Harrison
Browse files

drm/i915/perf: complete programming whitelisting for XEHPSDV 



We have an additional register to select which slices contribute to
OAG/OAG counter increments.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-16-umesh.nerlige.ramappa@intel.com
parent 01e74274

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -903,6 +903,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 


#define HAS_OA_BPC_REPORTING(dev_priv) \

	(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)

#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \

	(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)



/*

 * Set this flag, when platform requires 64K GTT page sizes or larger for

drivers/gpu/drm/i915/i915_pci.c

+1 −0
Original line number Diff line number Diff line
@@ -1024,6 +1024,7 @@ static const struct intel_device_info adl_p_info = { 
	.has_logical_ring_elsq = 1, \

	.has_mslice_steering = 1, \

	.has_oa_bpc_reporting = 1, \

	.has_oa_slice_contrib_limits = 1, \

	.has_rc6 = 1, \

	.has_reset_engine = 1, \

	.has_rps = 1, \

drivers/gpu/drm/i915/i915_perf.c

+13 −0
Original line number Diff line number Diff line
@@ -4261,6 +4261,11 @@ static const struct i915_range gen12_oa_b_counters[] = { 
	{}

};



static const struct i915_range xehp_oa_b_counters[] = {

	{ .start = 0xdc48, .end = 0xdc48 },	/* OAA_ENABLE_REG */

	{ .start = 0xdd00, .end = 0xdd48 },	/* OAG_LCE0_0 - OAA_LENABLE_REG */

};



static const struct i915_range gen7_oa_mux_regs[] = {

	{ .start = 0x91b8, .end = 0x91cc },	/* OA_PERFCNT[1-2], OA_PERFMATRIX */

	{ .start = 0x9800, .end = 0x9888 },	/* MICRO_BP0_0 - NOA_WRITE */
@@ -4335,6 +4340,12 @@ static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) 
	return reg_in_range_table(addr, gen12_oa_b_counters);

}



static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)

{

	return reg_in_range_table(addr, xehp_oa_b_counters) ||

		reg_in_range_table(addr, gen12_oa_b_counters);

}



static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

{

	return reg_in_range_table(addr, gen12_oa_mux_regs);
@@ -4847,6 +4858,8 @@ void i915_perf_init(struct drm_i915_private *i915) 
			perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;

		} else if (GRAPHICS_VER(i915) == 12) {

			perf->ops.is_valid_b_counter_reg =

				HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?

				xehp_is_valid_b_counter_addr :

				gen12_is_valid_b_counter_addr;

			perf->ops.is_valid_mux_reg =

				gen12_is_valid_mux_addr;

drivers/gpu/drm/i915/intel_device_info.h

+1 −0
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ enum intel_ppgtt_type { 
	func(has_media_ratio_mode); \

	func(has_mslice_steering); \

	func(has_oa_bpc_reporting); \

	func(has_oa_slice_contrib_limits); \

	func(has_one_eu_per_fuse_bit); \

	func(has_pxp); \

	func(has_rc6); \