Commit 01e74274 authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by John Harrison
Browse files

drm/i915/guc: Support OA when Wa_16011777198 is enabled 



On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.

v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset

v3: (Ashutosh)
- Just use intel_uc_uses_guc_rc

Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-15-umesh.nerlige.ramappa@intel.com
parent fa569804

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

+9 −0
Original line number Diff line number Diff line
@@ -128,6 +128,15 @@ enum slpc_media_ratio_mode { 
	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,

};



enum slpc_gucrc_mode {

	SLPC_GUCRC_MODE_HW = 0,

	SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,

	SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,

	SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,



	SLPC_GUCRC_MODE_MAX,

};



enum slpc_event_id {

	SLPC_EVENT_RESET = 0,

	SLPC_EVENT_SHUTDOWN = 1,

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

+66 −0
Original line number Diff line number Diff line
@@ -137,6 +137,17 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value) 
	return ret > 0 ? -EPROTO : ret;

}



static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)

{

	u32 request[] = {

		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,

		SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),

		id,

	};



	return intel_guc_send(guc, request, ARRAY_SIZE(request));

}



static bool slpc_is_running(struct intel_guc_slpc *slpc)

{

	return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -190,6 +201,15 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value) 
	return ret;

}



static int slpc_unset_param(struct intel_guc_slpc *slpc, u8 id)

{

	struct intel_guc *guc = slpc_to_guc(slpc);



	GEM_BUG_ON(id >= SLPC_MAX_PARAM);



	return guc_action_slpc_unset_param(guc, id);

}



static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)

{

	struct drm_i915_private *i915 = slpc_to_i915(slpc);
@@ -644,6 +664,52 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc) 
		slpc->boost_freq = slpc->rp0_freq;

}



/**

 * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode

 * @slpc: pointer to intel_guc_slpc.

 * @mode: new value of the mode.

 *

 * This function will override the GUCRC mode.

 *

 * Return: 0 on success, non-zero error code on failure.

 */

int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)

{

	int ret;

	struct drm_i915_private *i915 = slpc_to_i915(slpc);

	intel_wakeref_t wakeref;



	if (mode >= SLPC_GUCRC_MODE_MAX)

		return -EINVAL;



	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {

		ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);

		if (ret)

			drm_err(&i915->drm,

				"Override gucrc mode %d failed %d\n",

				mode, ret);

	}



	return ret;

}



int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)

{

	struct drm_i915_private *i915 = slpc_to_i915(slpc);

	intel_wakeref_t wakeref;

	int ret = 0;



	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {

		ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);

		if (ret)

			drm_err(&i915->drm,

				"Unsetting gucrc mode failed %d\n",

				ret);

	}



	return ret;

}



/*

 * intel_guc_slpc_enable() - Start SLPC

 * @slpc: pointer to intel_guc_slpc.

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h

+2 −0
Original line number Diff line number Diff line
@@ -44,5 +44,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val); 
void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);

void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);

void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);

int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);

int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);



#endif

drivers/gpu/drm/i915/i915_perf.c

+27 −0
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ 
#include "gt/intel_lrc.h"

#include "gt/intel_lrc_reg.h"

#include "gt/intel_ring.h"

#include "gt/uc/intel_guc_slpc.h"



#include "i915_drv.h"

#include "i915_file_private.h"
@@ -1582,6 +1583,15 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) 


	free_oa_buffer(stream);



	/*

	 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.

	 */

	if (intel_uc_uses_guc_rc(&gt->uc) &&

	    (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||

	     IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)))

		drm_WARN_ON(&gt->i915->drm,

			    intel_guc_slpc_unset_gucrc_mode(&gt->uc.guc.slpc));



	intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);

	intel_engine_pm_put(stream->engine);
@@ -3265,6 +3275,23 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, 
	intel_engine_pm_get(stream->engine);

	intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);



	/*

	 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes

	 * OA to lose the configuration state. Prevent this by overriding GUCRC

	 * mode.

	 */

	if (intel_uc_uses_guc_rc(&gt->uc) &&

	    (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||

	     IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {

		ret = intel_guc_slpc_override_gucrc_mode(&gt->uc.guc.slpc,

							 SLPC_GUCRC_MODE_GUCRC_NO_RC6);

		if (ret) {

			drm_dbg(&stream->perf->i915->drm,

				"Unable to override gucrc mode\n");

			goto err_config;

		}

	}



	ret = alloc_oa_buffer(stream);

	if (ret)

		goto err_oa_buf_alloc;