Commit 0fa72ed0 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/loongarch into irq/irqchip-next 



* irq/loongarch:
  : .
  : Merge the long awaited IRQ support for the LoongArch architecture.
  :
  : From the cover letter:
  :
  : "Currently, LoongArch based processors (e.g. Loongson-3A5000)
  : can only work together with LS7A chipsets. The irq chips in
  : LoongArch computers include CPUINTC (CPU Core Interrupt
  : Controller), LIOINTC (Legacy I/O Interrupt Controller),
  : EIOINTC (Extended I/O Interrupt Controller), PCH-PIC (Main
  : Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt
  : Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller)."
  :
  : Note that this comes with non-official, arch private ACPICA
  : definitions until the official ACPICA update is realeased.
  : .
  irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
  irqchip: Add LoongArch CPU interrupt controller support
  irqchip: Add Loongson Extended I/O interrupt controller support
  irqchip/loongson-liointc: Add ACPI init support
  irqchip/loongson-pch-msi: Add ACPI init support
  irqchip/loongson-pch-pic: Add ACPI init support
  irqchip: Add Loongson PCH LPC controller support
  LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
  LoongArch: Use ACPI_GENERIC_GSI for gsi handling
  genirq/generic_chip: Export irq_unmap_generic_chip
  ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
  APCI: irq: Add support for multiple GSI domains
  LoongArch: Provisionally add ACPICA data structures

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 2b0d7ab1 e8bba72b

arch/loongarch/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
config LOONGARCH

	bool

	default y

	select ACPI_GENERIC_GSI if ACPI

	select ACPI_SYSTEM_POWER_STATES_SUPPORT	if ACPI

	select ARCH_BINFMT_ELF_STATE

	select ARCH_ENABLE_MEMORY_HOTPLUG

arch/loongarch/include/asm/acpi.h

+142 −0
Original line number Diff line number Diff line
@@ -31,6 +31,148 @@ static inline bool acpi_has_cpu_in_madt(void) 


extern struct list_head acpi_wakeup_device_list;



/*

 * Temporary definitions until the core ACPICA code gets updated (see

 * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its

 * follow-ups for the "rationale").

 *

 * Once the "legal reasons" are cleared and that the code is merged,

 * this can be dropped entierely.

 */

#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))



#define LOONGARCH_ACPICA_EXT	1



#define	ACPI_MADT_TYPE_CORE_PIC		17

#define	ACPI_MADT_TYPE_LIO_PIC		18

#define	ACPI_MADT_TYPE_HT_PIC		19

#define	ACPI_MADT_TYPE_EIO_PIC		20

#define	ACPI_MADT_TYPE_MSI_PIC		21

#define	ACPI_MADT_TYPE_BIO_PIC		22

#define	ACPI_MADT_TYPE_LPC_PIC		23



/* Values for Version field above */



enum acpi_madt_core_pic_version {

	ACPI_MADT_CORE_PIC_VERSION_NONE = 0,

	ACPI_MADT_CORE_PIC_VERSION_V1 = 1,

	ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_lio_pic_version {

	ACPI_MADT_LIO_PIC_VERSION_NONE = 0,

	ACPI_MADT_LIO_PIC_VERSION_V1 = 1,

	ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_eio_pic_version {

	ACPI_MADT_EIO_PIC_VERSION_NONE = 0,

	ACPI_MADT_EIO_PIC_VERSION_V1 = 1,

	ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_ht_pic_version {

	ACPI_MADT_HT_PIC_VERSION_NONE = 0,

	ACPI_MADT_HT_PIC_VERSION_V1 = 1,

	ACPI_MADT_HT_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_bio_pic_version {

	ACPI_MADT_BIO_PIC_VERSION_NONE = 0,

	ACPI_MADT_BIO_PIC_VERSION_V1 = 1,

	ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_msi_pic_version {

	ACPI_MADT_MSI_PIC_VERSION_NONE = 0,

	ACPI_MADT_MSI_PIC_VERSION_V1 = 1,

	ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



enum acpi_madt_lpc_pic_version {

	ACPI_MADT_LPC_PIC_VERSION_NONE = 0,

	ACPI_MADT_LPC_PIC_VERSION_V1 = 1,

	ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



#pragma pack(1)



/* Core Interrupt Controller */



struct acpi_madt_core_pic {

	struct acpi_subtable_header header;

	u8 version;

	u32 processor_id;

	u32 core_id;

	u32 flags;

};



/* Legacy I/O Interrupt Controller */



struct acpi_madt_lio_pic {

	struct acpi_subtable_header header;

	u8 version;

	u64 address;

	u16 size;

	u8 cascade[2];

	u32 cascade_map[2];

};



/* Extend I/O Interrupt Controller */



struct acpi_madt_eio_pic {

	struct acpi_subtable_header header;

	u8 version;

	u8 cascade;

	u8 node;

	u64 node_map;

};



/* HT Interrupt Controller */



struct acpi_madt_ht_pic {

	struct acpi_subtable_header header;

	u8 version;

	u64 address;

	u16 size;

	u8 cascade[8];

};



/* Bridge I/O Interrupt Controller */



struct acpi_madt_bio_pic {

	struct acpi_subtable_header header;

	u8 version;

	u64 address;

	u16 size;

	u16 id;

	u16 gsi_base;

};



/* MSI Interrupt Controller */



struct acpi_madt_msi_pic {

	struct acpi_subtable_header header;

	u8 version;

	u64 msg_address;

	u32 start;

	u32 count;

};



/* LPC Interrupt Controller */



struct acpi_madt_lpc_pic {

	struct acpi_subtable_header header;

	u8 version;

	u64 address;

	u16 size;

	u8 cascade;

};



#pragma pack()



#endif



#endif /* !CONFIG_ACPI */



#define ACPI_TABLE_UPGRADE_MAX_PHYS ARCH_LOW_ADDRESS_LIMIT

arch/loongarch/include/asm/irq.h

+27 −24
Original line number Diff line number Diff line
@@ -35,9 +35,6 @@ static inline bool on_irq_stack(int cpu, unsigned long sp) 
	return (low <= sp && sp <= high);

}



int get_ipi_irq(void);

int get_pmc_irq(void);

int get_timer_irq(void);

void spurious_interrupt(void);



#define NR_IRQS_LEGACY 16
@@ -48,6 +45,14 @@ void arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_sel 
#define MAX_IO_PICS 2

#define NR_IRQS	(64 + (256 * MAX_IO_PICS))



struct acpi_vector_group {

	int node;

	int pci_segment;

	struct irq_domain *parent;

};

extern struct acpi_vector_group pch_group[MAX_IO_PICS];

extern struct acpi_vector_group msi_group[MAX_IO_PICS];



#define CORES_PER_EIO_NODE	4



#define LOONGSON_CPU_UART0_VEC		10 /* CPU UART0 */
@@ -79,15 +84,6 @@ void arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_sel 
extern int find_pch_pic(u32 gsi);

extern int eiointc_get_node(int id);



static inline void eiointc_enable(void)

{

	uint64_t misc;



	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);

	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;

	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);

}



struct acpi_madt_lio_pic;

struct acpi_madt_eio_pic;

struct acpi_madt_ht_pic;
@@ -95,21 +91,29 @@ struct acpi_madt_bio_pic; 
struct acpi_madt_msi_pic;

struct acpi_madt_lpc_pic;



struct irq_domain *loongarch_cpu_irq_init(void);



struct irq_domain *liointc_acpi_init(struct irq_domain *parent,

int liointc_acpi_init(struct irq_domain *parent,

					struct acpi_madt_lio_pic *acpi_liointc);

struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,

int eiointc_acpi_init(struct irq_domain *parent,

					struct acpi_madt_eio_pic *acpi_eiointc);



struct irq_domain *htvec_acpi_init(struct irq_domain *parent,

					struct acpi_madt_ht_pic *acpi_htvec);

struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,

int pch_lpc_acpi_init(struct irq_domain *parent,

					struct acpi_madt_lpc_pic *acpi_pchlpc);

struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,

#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)

int pch_msi_acpi_init(struct irq_domain *parent,

					struct acpi_madt_msi_pic *acpi_pchmsi);

struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,

#else

static inline int pch_msi_acpi_init(struct irq_domain *parent,

					struct acpi_madt_msi_pic *acpi_pchmsi)

{

	return 0;

}

#endif

int pch_pic_acpi_init(struct irq_domain *parent,

					struct acpi_madt_bio_pic *acpi_pchpic);

int find_pch_pic(u32 gsi);

struct fwnode_handle *get_pch_msi_handle(int pci_segment);



extern struct acpi_madt_lio_pic *acpi_liointc;

extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -119,11 +123,10 @@ extern struct acpi_madt_lpc_pic *acpi_pchlpc; 
extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];

extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];



extern struct irq_domain *cpu_domain;

extern struct irq_domain *liointc_domain;

extern struct irq_domain *pch_lpc_domain;

extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];

extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];

extern struct fwnode_handle *cpuintc_handle;

extern struct fwnode_handle *liointc_handle;

extern struct fwnode_handle *pch_lpc_handle;

extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];



extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);

arch/loongarch/kernel/acpi.c

+0 −65
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ EXPORT_SYMBOL(acpi_pci_disabled); 
int acpi_strict = 1; /* We have no workarounds on LoongArch */

int num_processors;

int disabled_cpus;

enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;



u64 acpi_saved_sp;
@@ -33,70 +32,6 @@ u64 acpi_saved_sp; 


#define PREFIX			"ACPI: "



int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)

{

	if (irqp != NULL)

		*irqp = acpi_register_gsi(NULL, gsi, -1, -1);

	return (*irqp >= 0) ? 0 : -EINVAL;

}

EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);



int acpi_isa_irq_to_gsi(unsigned int isa_irq, u32 *gsi)

{

	if (gsi)

		*gsi = isa_irq;

	return 0;

}



/*

 * success: return IRQ number (>=0)

 * failure: return < 0

 */

int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)

{

	struct irq_fwspec fwspec;



	switch (gsi) {

	case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:

		fwspec.fwnode = liointc_domain->fwnode;

		fwspec.param[0] = gsi - GSI_MIN_CPU_IRQ;

		fwspec.param_count = 1;



		return irq_create_fwspec_mapping(&fwspec);



	case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:

		if (!pch_lpc_domain)

			return -EINVAL;



		fwspec.fwnode = pch_lpc_domain->fwnode;

		fwspec.param[0] = gsi - GSI_MIN_LPC_IRQ;

		fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);

		fwspec.param_count = 2;



		return irq_create_fwspec_mapping(&fwspec);



	case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:

		if (!pch_pic_domain[0])

			return -EINVAL;



		fwspec.fwnode = pch_pic_domain[0]->fwnode;

		fwspec.param[0] = gsi - GSI_MIN_PCH_IRQ;

		fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;

		fwspec.param_count = 2;



		return irq_create_fwspec_mapping(&fwspec);

	}



	return -EINVAL;

}

EXPORT_SYMBOL_GPL(acpi_register_gsi);



void acpi_unregister_gsi(u32 gsi)

{



}

EXPORT_SYMBOL_GPL(acpi_unregister_gsi);



void __init __iomem * __acpi_map_table(unsigned long phys, unsigned long size)

{

arch/loongarch/kernel/irq.c

+51 −7
Original line number Diff line number Diff line
@@ -25,12 +25,8 @@ DEFINE_PER_CPU(unsigned long, irq_stack); 
DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);

EXPORT_PER_CPU_SYMBOL(irq_stat);



struct irq_domain *cpu_domain;

struct irq_domain *liointc_domain;

struct irq_domain *pch_lpc_domain;

struct irq_domain *pch_msi_domain[MAX_IO_PICS];

struct irq_domain *pch_pic_domain[MAX_IO_PICS];



struct acpi_vector_group pch_group[MAX_IO_PICS];

struct acpi_vector_group msi_group[MAX_IO_PICS];

/*

 * 'what should we do if we get a hw irq event on an illegal vector'.

 * each architecture has to answer this themselves.
@@ -56,6 +52,51 @@ int arch_show_interrupts(struct seq_file *p, int prec) 
	return 0;

}



static int __init early_pci_mcfg_parse(struct acpi_table_header *header)

{

	struct acpi_table_mcfg *mcfg;

	struct acpi_mcfg_allocation *mptr;

	int i, n;



	if (header->length < sizeof(struct acpi_table_mcfg))

		return -EINVAL;



	n = (header->length - sizeof(struct acpi_table_mcfg)) /

					sizeof(struct acpi_mcfg_allocation);

	mcfg = (struct acpi_table_mcfg *)header;

	mptr = (struct acpi_mcfg_allocation *) &mcfg[1];



	for (i = 0; i < n; i++, mptr++) {

		msi_group[i].pci_segment = mptr->pci_segment;

		pch_group[i].node = msi_group[i].node = (mptr->address >> 44) & 0xf;

	}



	return 0;

}



static void __init init_vec_parent_group(void)

{

	int i;



	for (i = 0; i < MAX_IO_PICS; i++) {

		msi_group[i].pci_segment = -1;

		msi_group[i].node = -1;

		pch_group[i].node = -1;

	}



	acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);

}



static int __init get_ipi_irq(void)

{

	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);



	if (d)

		return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);



	return -EINVAL;

}



void __init init_IRQ(void)

{

	int i;
@@ -69,9 +110,12 @@ void __init init_IRQ(void) 
	clear_csr_ecfg(ECFG0_IM);

	clear_csr_estat(ESTATF_IP);



	init_vec_parent_group();

	irqchip_init();

#ifdef CONFIG_SMP

	ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;

	ipi_irq = get_ipi_irq();

	if (ipi_irq < 0)

		panic("IPI IRQ mapping failed\n");

	irq_set_percpu_devid(ipi_irq);

	r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);

	if (r < 0)