Commit 2b0d7ab1 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/renesas-irqc into irq/irqchip-next 



* irq/renesas-irqc:
  : .
  : New Renesas RZ/G2L IRQC driver from Lad Prabhakar, equipped with
  : its companion GPIO driver.
  : .
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC
  gpio: thunderx: Don't directly include asm-generic/msi.h
  pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ
  gpio: gpiolib: Allow free() callback to be overridden
  irqchip: Add RZ/G2L IA55 Interrupt Controller driver
  dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller
  gpio: Remove dynamic allocation from populate_parent_alloc_arg()

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents d4a930a0 8cfc90ec

Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

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+134 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  IA55 performs various interrupt controls including synchronization for the external

  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral

  interrupts output by each IP. And it notifies the interrupt to the GIC

    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts

    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts

    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and

      stand-up edge detection interrupts)



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}

          - renesas,r9a07g054-irqc    # RZ/V2L

      - const: renesas,rzg2l-irqc



  '#interrupt-cells':

    description: The first cell should contain external interrupt number (IRQ0-7) and the

                 second cell is used to specify the flag.

    const: 2



  '#address-cells':

    const: 0



  interrupt-controller: true



  reg:

    maxItems: 1



  interrupts:

    maxItems: 41



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: clk

      - const: pclk



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



required:

  - compatible

  - '#interrupt-cells'

  - '#address-cells'

  - interrupt-controller

  - reg

  - interrupts

  - clocks

  - clock-names

  - power-domains

  - resets



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/r9a07g044-cpg.h>



    irqc: interrupt-controller@110a0000 {

            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";

            reg = <0x110a0000 0x10000>;

            #interrupt-cells = <2>;

            #address-cells = <0>;

            interrupt-controller;

            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,

                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;

            clock-names = "clk", "pclk";

            power-domains = <&cpg>;

            resets = <&cpg R9A07G044_IA55_RESETN>;

    };

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+15 −0
Original line number Diff line number Diff line
@@ -47,6 +47,17 @@ properties: 
  gpio-ranges:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    description:

      The first cell contains the global GPIO port index, constructed using the

      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the

      second cell is used to specify the flag.

      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is

      being used as an interrupt.



  clocks:

    maxItems: 1
@@ -110,6 +121,8 @@ required: 
  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

  - interrupt-controller

  - '#interrupt-cells'

  - clocks

  - power-domains

  - resets
@@ -126,6 +139,8 @@ examples: 
            gpio-controller;

            #gpio-cells = <2>;

            gpio-ranges = <&pinctrl 0 0 392>;

            interrupt-controller;

            #interrupt-cells = <2>;

            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;

            resets = <&cpg R9A07G044_GPIO_RSTN>,

                     <&cpg R9A07G044_GPIO_PORT_RESETN>,

drivers/gpio/gpio-msc313.c

+6 −9
Original line number Diff line number Diff line
@@ -550,15 +550,12 @@ static struct irq_chip msc313_gpio_irqchip = { 
 * so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell

 * that puts GIC_SPI into the first cell.

 */

static void *msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc,

static int msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc,

					      union gpio_irq_fwspec *gfwspec,

					      unsigned int parent_hwirq,

					      unsigned int parent_type)

{

	struct irq_fwspec *fwspec;



	fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);

	if (!fwspec)

		return NULL;

	struct irq_fwspec *fwspec = &gfwspec->fwspec;



	fwspec->fwnode = gc->irq.parent_domain->fwnode;

	fwspec->param_count = 3;
@@ -566,7 +563,7 @@ static void *msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc, 
	fwspec->param[1] = parent_hwirq;

	fwspec->param[2] = parent_type;



	return fwspec;

	return 0;

}



static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip,

drivers/gpio/gpio-tegra.c

+6 −9
Original line number Diff line number Diff line
@@ -443,15 +443,12 @@ static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 
	return 0;

}



static void *tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,

static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,

					     union gpio_irq_fwspec *gfwspec,

					     unsigned int parent_hwirq,

					     unsigned int parent_type)

{

	struct irq_fwspec *fwspec;



	fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);

	if (!fwspec)

		return NULL;

	struct irq_fwspec *fwspec = &gfwspec->fwspec;



	fwspec->fwnode = chip->irq.parent_domain->fwnode;

	fwspec->param_count = 3;
@@ -459,7 +456,7 @@ static void *tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip, 
	fwspec->param[1] = parent_hwirq;

	fwspec->param[2] = parent_type;



	return fwspec;

	return 0;

}



#ifdef CONFIG_PM_SLEEP

drivers/gpio/gpio-tegra186.c

+6 −9
Original line number Diff line number Diff line
@@ -621,16 +621,13 @@ static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 
	return 0;

}



static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,

static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,

						union gpio_irq_fwspec *gfwspec,

						unsigned int parent_hwirq,

						unsigned int parent_type)

{

	struct tegra_gpio *gpio = gpiochip_get_data(chip);

	struct irq_fwspec *fwspec;



	fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);

	if (!fwspec)

		return NULL;

	struct irq_fwspec *fwspec = &gfwspec->fwspec;



	fwspec->fwnode = chip->irq.parent_domain->fwnode;

	fwspec->param_count = 3;
@@ -638,7 +635,7 @@ static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 
	fwspec->param[1] = parent_hwirq;

	fwspec->param[2] = parent_type;



	return fwspec;

	return 0;

}



static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,