Commit 0ccb8385 authored by Liu Ying's avatar Liu Ying Committed by Vinod Koul
Browse files

dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp 



Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.

Cc: Guido Günther <agx@sigxcpu.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarGuido Günther <agx@sigxcpu.org>
Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
Link: https://lore.kernel.org/r/20220419010852.452169-5-victor.liu@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f9b0593d

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml

+38 −3
Original line number Diff line number Diff line
@@ -14,10 +14,14 @@ description: | 
  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

  electrical signals for DSI.



  The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work

  in either MIPI-DSI PHY mode or LVDS PHY mode.



properties:

  compatible:

    enum:

      - fsl,imx8mq-mipi-dphy

      - fsl,imx8qxp-mipi-dphy



  reg:

    maxItems: 1
@@ -40,6 +44,11 @@ properties: 
  "#phy-cells":

    const: 0



  fsl,syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      A phandle which points to Control and Status Registers(CSR) module.



  power-domains:

    maxItems: 1
@@ -48,11 +57,37 @@ required: 
  - reg

  - clocks

  - clock-names

  - "#phy-cells"

  - power-domains



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8mq-mipi-dphy

    then:

      properties:

        fsl,syscon: false



      required:

        - assigned-clocks

        - assigned-clock-parents

        - assigned-clock-rates

  - "#phy-cells"

  - power-domains



  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qxp-mipi-dphy

    then:

      properties:

        assigned-clocks: false

        assigned-clock-parents: false

        assigned-clock-rates: false



      required:

        - fsl,syscon



additionalProperties: false