Commit f9b0593d authored by Liu Ying's avatar Liu Ying Committed by Vinod Koul
Browse files

dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema 



This patch converts the mixel,mipi-dsi-phy binding to
DT schema format using json-schema.

Comparing to the plain text version, the new binding adds
the 'assigned-clocks', 'assigned-clock-parents' and
'assigned-clock-rates' properites, otherwise 'make dtbs_check'
would complain that there are mis-matches.  Also, the new
binding requires the 'power-domains' property since all potential
SoCs that embed this PHY would provide a power domain for it.
The example of the new binding takes reference to the latest
dphy node in imx8mq.dtsi.

Cc: Guido Günther <agx@sigxcpu.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarGuido Günther <agx@sigxcpu.org>
Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
Link: https://lore.kernel.org/r/20220419010852.452169-4-victor.liu@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 3abfaefb

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt

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Mixel DSI PHY for i.MX8



The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

electrical signals for DSI.



Required properties:

- compatible: Must be:

  - "fsl,imx8mq-mipi-dphy"

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must contain the following entries:

  - "phy_ref": phandle and specifier referring to the DPHY ref clock

- reg: the register range of the PHY controller

- #phy-cells: number of cells in PHY, as defined in

  Documentation/devicetree/bindings/phy/phy-bindings.txt

  this must be <0>



Optional properties:

- power-domains: phandle to power domain



Example:

	dphy: dphy@30a0030 {

		compatible = "fsl,imx8mq-mipi-dphy";

		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

		clock-names = "phy_ref";

		reg = <0x30a00300 0x100>;

		power-domains = <&pd_mipi0>;

		#phy-cells = <0>;

        };

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mixel DSI PHY for i.MX8



maintainers:

  - Guido Günther <agx@sigxcpu.org>



description: |

  The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

  electrical signals for DSI.



properties:

  compatible:

    enum:

      - fsl,imx8mq-mipi-dphy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: phy_ref



  assigned-clocks:

    maxItems: 1



  assigned-clock-parents:

    maxItems: 1



  assigned-clock-rates:

    maxItems: 1



  "#phy-cells":

    const: 0



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - assigned-clocks

  - assigned-clock-parents

  - assigned-clock-rates

  - "#phy-cells"

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mq-clock.h>

    dphy: dphy@30a0030 {

        compatible = "fsl,imx8mq-mipi-dphy";

        reg = <0x30a00300 0x100>;

        clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

        clock-names = "phy_ref";

        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;

        assigned-clock-rates = <24000000>;

        #phy-cells = <0>;

        power-domains = <&pgc_mipi>;

    };