Commit 0b8bf9cb authored by Marc Bevand's avatar Marc Bevand Committed by Borislav Petkov
Browse files

EDAC/amd64: Add support for family 19h, models 50h-5fh



Add the new family 19h models 50h-5fh PCI IDs (device 18h functions 0
and 6) to support Ryzen 5000 APUs ("Cezanne").

Signed-off-by: default avatarMarc Bevand <m@zorinaq.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Link: https://lore.kernel.org/r/20211221233112.556927-1-m@zorinaq.com
parent e2be5955
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+15 −0
Original line number Diff line number Diff line
@@ -2660,6 +2660,16 @@ static struct amd64_family_type family_types[] = {
			.dbam_to_cs		= f17_addr_mask_to_cs_size,
		}
	},
	[F19_M50H_CPUS] = {
		.ctl_name = "F19h_M50h",
		.f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
		.f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6,
		.max_mcs = 2,
		.ops = {
			.early_channel_count	= f17_early_channel_count,
			.dbam_to_cs		= f17_addr_mask_to_cs_size,
		}
	},
};

/*
@@ -3706,6 +3716,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
			pvt->ops = &family_types[F17_M70H_CPUS].ops;
			fam_type->ctl_name = "F19h_M20h";
			break;
		} else if (pvt->model >= 0x50 && pvt->model <= 0x5f) {
			fam_type = &family_types[F19_M50H_CPUS];
			pvt->ops = &family_types[F19_M50H_CPUS].ops;
			fam_type->ctl_name = "F19h_M50h";
			break;
		} else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) {
			fam_type = &family_types[F19_M10H_CPUS];
			pvt->ops = &family_types[F19_M10H_CPUS].ops;
+3 −0
Original line number Diff line number Diff line
@@ -128,6 +128,8 @@
#define PCI_DEVICE_ID_AMD_19H_DF_F6	0x1656
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670

/*
 * Function 1 - Address Map
@@ -301,6 +303,7 @@ enum amd_families {
	F17_M70H_CPUS,
	F19_CPUS,
	F19_M10H_CPUS,
	F19_M50H_CPUS,
	NUM_FAMILIES,
};