Commit 0a8e7330 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-tegra-5.13' of... 

Merge tag 'memory-controller-drv-tegra-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.13 - Tegra SoC

1. Few cleanups.
2. Add debug statistics to Tegra20 memory controller.
3. Update bindings and convert to dtschema.  This update is not
   backwards compatible (ABI break) however the broken part was added
   recently (v5.11) and there are no users of it yet.

* tag 'memory-controller-drv-tegra-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  dt-bindings: memory: tegra20: mc: Convert to schema
  dt-bindings: memory: tegra124: emc: Replace core regulator with power domain
  dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
  dt-bindings: memory: tegra20: emc: Replace core regulator with power domain
  memory: tegra: Print out info-level once per driver probe
  memory: tegra20: Protect debug code with a lock
  memory: tegra20: Correct comment to MC_STAT registers writes
  memory: tegra20: Add debug statistics
  memory: tegra: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE

Link: https://lore.kernel.org/r/20210407161333.73013-2-krzysztof.kozlowski@canonical.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f8e547f5 d8d5cbc6

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml

+4 −3
Original line number Diff line number Diff line
@@ -37,9 +37,10 @@ properties: 
    description:

      phandle of the memory controller node



  core-supply:

  power-domains:

    maxItems: 1

    description:

      Phandle of voltage regulator of the SoC "core" power domain.

      Phandle of the SoC "core" power domain.



  operating-points-v2:

    description:
@@ -370,7 +371,7 @@ examples: 


        nvidia,memory-controller = <&mc>;

        operating-points-v2 = <&dvfs_opp_table>;

        core-supply = <&vdd_core>;

        power-domains = <&domain>;



        #interconnect-cells = <0>;

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt

+2 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ For each opp entry in 'operating-points-v2' table: 
	matches, the OPP gets enabled.



Optional properties:

- core-supply: Phandle of voltage regulator of the SoC "core" power domain.

- power-domains: Phandle of the SoC "core" power domain.



Child device nodes describe the memory settings for different configurations and clock rates.
@@ -48,7 +48,7 @@ Example: 
		interrupts = <0 78 0x04>;

		clocks = <&tegra_car TEGRA20_CLK_EMC>;

		nvidia,memory-controller = <&mc>;

		core-supply = <&core_vdd_reg>;

		power-domains = <&domain>;

		operating-points-v2 = <&opp_table>;

	}

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt

deleted100644 → 0
+0 −40
Original line number Diff line number Diff line 
NVIDIA Tegra20 MC(Memory Controller)



Required properties:

- compatible : "nvidia,tegra20-mc-gart"

- reg : Should contain 2 register ranges: physical base address and length of

  the controller's registers and the GART aperture respectively.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts : Should contain MC General interrupt.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>

  or in the TRM documentation.

- #iommu-cells: Should be 0. This cell represents the number of cells in an

  IOMMU specifier needed to encode an address. GART supports only a single

  address space that is shared by all devices, therefore no additional

  information needed for the address encoding.

- #interconnect-cells : Should be 1. This cell represents memory client.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.



Example:

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 0x04>;

		#reset-cells = <1>;

		#iommu-cells = <0>;

		#interconnect-cells = <1>;

	};



	video-codec@6001a000 {

		compatible = "nvidia,tegra20-vde";

		...

		resets = <&mc TEGRA20_MC_RESET_VDE>;

		iommus = <&mc>;

	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

0 → 100644
+79 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra20 SoC Memory Controller



maintainers:

  - Dmitry Osipenko <digetx@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>



description: |

  The Tegra20 Memory Controller merges request streams from various client

  interfaces into request stream(s) for the various memory target devices,

  and returns response data to the various clients. The Memory Controller

  has a configurable arbitration algorithm to allow the user to fine-tune

  performance among the various clients.



  Tegra20 Memory Controller includes the GART (Graphics Address Relocation

  Table) which allows Memory Controller to provide a linear view of a

  fragmented memory pages.



properties:

  compatible:

    const: nvidia,tegra20-mc-gart



  reg:

    items:

      - description: controller registers

      - description: GART registers



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: mc



  interrupts:

    maxItems: 1



  "#reset-cells":

    const: 1



  "#iommu-cells":

    const: 0



  "#interconnect-cells":

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#reset-cells"

  - "#iommu-cells"

  - "#interconnect-cells"



additionalProperties: false



examples:

  - |

    memory-controller@7000f000 {

        compatible = "nvidia,tegra20-mc-gart";

        reg = <0x7000f000 0x400>,	/* Controller registers */

              <0x58000000 0x02000000>;	/* GART aperture */

        clocks = <&clock_controller 32>;

        clock-names = "mc";



        interrupts = <0 77 4>;



        #iommu-cells = <0>;

        #reset-cells = <1>;

        #interconnect-cells = <1>;

    };

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml

+4 −3
Original line number Diff line number Diff line
@@ -39,9 +39,10 @@ properties: 
    description:

      Phandle of the Memory Controller node.



  core-supply:

  power-domains:

    maxItems: 1

    description:

      Phandle of voltage regulator of the SoC "core" power domain.

      Phandle of the SoC "core" power domain.



  operating-points-v2:

    description:
@@ -241,7 +242,7 @@ examples: 


        nvidia,memory-controller = <&mc>;

        operating-points-v2 = <&dvfs_opp_table>;

        core-supply = <&vdd_core>;

        power-domains = <&domain>;



        #interconnect-cells = <0>;