Commit f8e547f5 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-5.13' of... 

Merge tag 'memory-controller-drv-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.13

1. OMAP: fix unlikely but possible out of bounds read.
2. PL353: fix mask used in setting ECC page_size in config register.
3. Minor cleanup: Freescale Corenet.

* tag 'memory-controller-drv-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: pl353: fix mask of ECC page_size config register
  memory: fsl-corenet-cf: Remove redundant dev_err call in ccf_probe()
  memory: gpmc: fix out of bounds read and dereference on gpmc_cs[]

Link: https://lore.kernel.org/r/20210407161333.73013-1-krzysztof.kozlowski@canonical.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 4a3c8895 25dcca7f

drivers/memory/fsl-corenet-cf.c

+1 −3
Original line number Diff line number Diff line
@@ -192,10 +192,8 @@ static int ccf_probe(struct platform_device *pdev) 
	}



	ccf->regs = devm_ioremap_resource(&pdev->dev, r);

	if (IS_ERR(ccf->regs)) {

		dev_err(&pdev->dev, "%s: can't map mem resource\n", __func__);

	if (IS_ERR(ccf->regs))

		return PTR_ERR(ccf->regs);

	}



	ccf->dev = &pdev->dev;

	ccf->info = match->data;

drivers/memory/omap-gpmc.c

+5 −2
Original line number Diff line number Diff line
@@ -1009,8 +1009,8 @@ EXPORT_SYMBOL(gpmc_cs_request); 


void gpmc_cs_free(int cs)

{

	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];

	struct resource *res = &gpmc->mem;

	struct gpmc_cs_data *gpmc;

	struct resource *res;



	spin_lock(&gpmc_mem_lock);

	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
@@ -1018,6 +1018,9 @@ void gpmc_cs_free(int cs) 
		spin_unlock(&gpmc_mem_lock);

		return;

	}

	gpmc = &gpmc_cs[cs];

	res = &gpmc->mem;



	gpmc_cs_disable_mem(cs);

	if (res->flags)

		release_resource(res);

drivers/memory/pl353-smc.c

+1 −1
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ 
/* ECC memory config register specific constants */

#define PL353_SMC_ECC_MEMCFG_MODE_MASK	0xC

#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT	2

#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0xC

#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0x3



#define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */ \

				 (2 << 21))	/* UpdateRegs operation */